Utilize BIT macro everywhere

bdk/soc/clock.c

@@ -20,17 +20,6 @@
 #include <storage/sdmmc.h>
 #include <utils/util.h>
 
-/*
- * CLOCK Peripherals:
- * L   0 -  31
- * H  32 -  63
- * U  64 -  95
- * V  96 - 127
- * W 128 - 159
- * X 160 - 191
- * Y 192 - 223
- */
-
 /* clock_t: reset, enable, source, index, clk_src, clk_div */
 
 static const clock_t _clock_uart[] = {
@@ -86,7 +75,7 @@ static clock_t _clock_coresight = {
 };
 
 static clock_t _clock_pwm = {
-	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM,    CLK_L_PWM,      6, 4 // Fref: 6.2MHz.
+	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM,    CLK_L_PWM,      6, 4 // Fref: 6.4MHz. Stock PLLP / 54: 7.55MHz.
 };
 
 static clock_t _clock_sdmmc_legacy_tm = {
@@ -96,30 +85,31 @@ static clock_t _clock_sdmmc_legacy_tm = {
 void clock_enable(const clock_t *clk)
 {
 	// Put clock into reset.
-	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
 	// Disable.
-	CLOCK(clk->enable) &= ~(1 << clk->index);
+	CLOCK(clk->enable) &= ~BIT(clk->index);
 	// Configure clock source if required.
 	if (clk->source)
 		CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
 	// Enable.
-	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index);
 	usleep(2);
 
 	// Take clock off reset.
-	CLOCK(clk->reset) &= ~(1 << clk->index);
+	CLOCK(clk->reset) &= ~BIT(clk->index);
 }
 
 void clock_disable(const clock_t *clk)
 {
 	// Put clock into reset.
-	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
 	// Disable.
-	CLOCK(clk->enable) &= ~(1 << clk->index);
+	CLOCK(clk->enable) &= ~BIT(clk->index);
 }
 
 void clock_enable_fuse(bool enable)
 {
+	// Enable Fuse registers visibility.
 	CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
 }
 
@@ -133,7 +123,7 @@ void clock_disable_uart(u32 idx)
 	clock_disable(&_clock_uart[idx]);
 }
 
-#define UART_SRC_CLK_DIV_EN (1 << 24)
+#define UART_SRC_CLK_DIV_EN BIT(24)
 
 int clock_uart_use_src_div(u32 idx, u32 baud)
 {
@@ -281,7 +271,7 @@ void clock_enable_pllc(u32 divn)
 	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
 
 	// Disable PLL and IDDQ in case they are on.
-	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE)   &= ~PLLCX_BASE_ENABLE;
 	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
 	usleep(10);
 
@@ -294,7 +284,7 @@ void clock_enable_pllc(u32 divn)
 		;
 
 	// Disable PLLC_OUT1, enable reset and set div to 1.5.
-	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = BIT(8);
 
 	// Enable PLLC_OUT1 and bring it out of reset.
 	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
@@ -304,15 +294,15 @@ void clock_enable_pllc(u32 divn)
 void clock_disable_pllc()
 {
 	// Disable PLLC and PLLC_OUT1.
-	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
-	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
-	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT)    &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE)   &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE)   |= PLLCX_BASE_REF_DIS;
 	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
-	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC)   |= PLLC_MISC_RESET;
 	usleep(10);
 }
 
-#define PLLC4_ENABLED (1 << 31)
+#define PLLC4_ENABLED BIT(31)
 #define PLLC4_IN_USE  (~PLLC4_ENABLED)
 
 u32 pllc4_enabled = 0;
@@ -365,14 +355,14 @@ static void _clock_disable_pllc4(u32 mask)
 void clock_enable_pllu()
 {
 	// Configure PLLU.
-	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= (1 << 29); // Disable reference clock.
-	u32 pllu_cfg = (CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & 0xFFE00000) | (1 << 24) | (1 << 16) | (0x19 << 8) | 2;
+	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= BIT(29); // Disable reference clock.
+	u32 pllu_cfg = (CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & 0xFFE00000) | BIT(24) | (1 << 16) | (0x19 << 8) | 2;
 	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg;
-	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | (1 << 30); // Enable.
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | PLLCX_BASE_ENABLE; // Enable.
 
 	// Wait for PLL to stabilize.
 	u32 timeout = (u32)TMR(TIMERUS_CNTR_1US) + 1300;
-	while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & (1 << 27))) // PLL_LOCK.
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & PLLCX_BASE_LOCK)) // PLL_LOCK.
 		if ((u32)TMR(TIMERUS_CNTR_1US) > timeout)
 			break;
 	usleep(10);
@@ -515,7 +505,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
 static void _clock_sdmmc_config_legacy_tm()
 {
 	clock_t *clk = &_clock_sdmmc_legacy_tm;
-	if (!(CLOCK(clk->enable) & (1 << clk->index)))
+	if (!(CLOCK(clk->enable) & BIT(clk->index)))
 		clock_enable(clk);
 }
 
@@ -600,7 +590,7 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
 
 	// Enable PLLC4 if in use by any SDMMC.
 	if (source)
-		_clock_enable_pllc4(1 << id);
+		_clock_enable_pllc4(BIT(id));
 
 	// Set SDMMC legacy timeout clock.
 	_clock_sdmmc_config_legacy_tm();
@@ -724,5 +714,5 @@ void clock_sdmmc_disable(u32 id)
 	_clock_sdmmc_set_reset(id);
 	_clock_sdmmc_clear_enable(id);
 	_clock_sdmmc_is_reset(id);
-	_clock_disable_pllc4(1 << id);
+	_clock_disable_pllc4(BIT(id));
 }