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Utilize BIT macro everywhere

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This commit is contained in:
CTCaer
2020-11-26 01:41:45 +02:00
parent 94486873c1
commit cabaa6cfb8
43 changed files with 517 additions and 515 deletions
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2
bdk/mem/emc.h
View File

@@ -232,7 +232,7 @@
#define EMC_COMP_PAD_SW_CTRL 0x57c
#define EMC_REQ_CTRL 0x2b0
#define EMC_EMC_STATUS 0x2b4
#define EMC_STATUS_MRR_DIVLD (1 << 20)
#define EMC_STATUS_MRR_DIVLD BIT(20)
#define EMC_CFG_2 0x2b8
#define EMC_CFG_DIG_DLL 0x2bc
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0

12
bdk/mem/mc_t210.h
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@@ -503,14 +503,14 @@
#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L2 (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L3 (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU (1 << 22)
#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU BIT(22)
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK (1 << 23)
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK (1 << 24)
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK BIT(23)
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK BIT(24)
#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH (1 << 25)
#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH (1 << 26)
#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH BIT(25)
#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH BIT(26)
#define SEC_CARVEOUT_CFG_IS_WPR (1 << 27)
#define SEC_CARVEOUT_CFG_IS_WPR BIT(27)
#endif

17
bdk/mem/sdram.c
View File

@@ -86,13 +86,18 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
{
emc_mr_data_t data;
// Device 0.
_sdram_req_mrr_data((1 << 31) | (mrx << 16), EMC_CHAN0);
/*
* When a dram chip has only one rank, then the info from the 2 ranks differs.
* Info not matching is only allowed on different channels.
*/
// Get Device 0 (Rank 0) info from both dram chips (channels).
_sdram_req_mrr_data(BIT(31) | (mrx << 16), EMC_CHAN0);
data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
// Device 1.
_sdram_req_mrr_data((1 << 30) | (mrx << 16), EMC_CHAN1);
// Get Device 1 (Rank 1) info from both dram chips (channels).
_sdram_req_mrr_data(BIT(30) | (mrx << 16), EMC_CHAN1);
data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
@@ -545,7 +550,7 @@ break_nosleep:
EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
// Patch BootROM.
if (params->boot_rom_patch_control & (1 << 31))
if (params->boot_rom_patch_control & BIT(31))
{
*(vu32 *)(APB_MISC_BASE + params->boot_rom_patch_control * 4) = params->boot_rom_patch_data;
MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update.
@@ -765,7 +770,7 @@ sdram_params_t *sdram_get_params_patched()
sdram_params_t *sdram_params = sdram_get_params();
// Disable Warmboot signature check.
sdram_params->boot_rom_patch_control = (1 << 31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
sdram_params->boot_rom_patch_control = BIT(31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
sdram_params->boot_rom_patch_data = IPATCH_CONFIG(0x10459E, 0x2000);
/*
// Disable SBK lock.

2
bdk/mem/sdram_config.inl
View File

@@ -17,7 +17,7 @@
#define DRAM_CFG_SIZE 1896
#define DRAM_ID(x) (1 << (x))
#define DRAM_ID(x) BIT(x)
#define DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH 0
#define DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN 1