Utilize BIT macro everywhere
This commit is contained in:
CTCaer
16
bdk/gfx/di.c
16
bdk/gfx/di.c
@@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -77,9 +77,9 @@ void display_init()
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz).
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// Disable deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
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// Bring every IO rail out of deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
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// Config LCD and Backlight pins.
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN
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@@ -255,7 +255,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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display_backlight_brightness(0, 1000);
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DSI(_DSIREG(DSI_WR_DATA)) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE;
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
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@@ -324,7 +324,7 @@ skip_panel_deinit:
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode.
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}
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void display_end() { _display_panel_and_hw_end(false); };
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@@ -386,7 +386,7 @@ u32 *display_init_framebuffer_log()
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void display_activate_console()
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{
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
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DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
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DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
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DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
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@@ -407,7 +407,7 @@ void display_activate_console()
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void display_deactivate_console()
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{
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
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for (u32 i = 0xFFFF; i > 0xFF7F; i--)
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{
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147
bdk/gfx/di.h
147
bdk/gfx/di.h
@@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -42,11 +42,11 @@
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#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
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#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
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#define SYNCPT_CNTRL_NO_STALL (1 << 8)
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#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
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#define SYNCPT_CNTRL_SOFT_RESET BIT(0)
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#define SYNCPT_CNTRL_NO_STALL BIT(8)
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#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
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#define SYNCPT_VSYNC_ENABLE (1 << 8)
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#define SYNCPT_VSYNC_ENABLE BIT(8)
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#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
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@@ -57,42 +57,42 @@
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#define DISP_CTRL_MODE_MASK (3 << 5)
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#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
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#define PW0_ENABLE (1 << 0)
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#define PW1_ENABLE (1 << 2)
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#define PW2_ENABLE (1 << 4)
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#define PW3_ENABLE (1 << 6)
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#define PW4_ENABLE (1 << 8)
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#define PM0_ENABLE (1 << 16)
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#define PM1_ENABLE (1 << 18)
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#define PW0_ENABLE BIT(0)
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#define PW1_ENABLE BIT(2)
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#define PW2_ENABLE BIT(4)
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#define PW3_ENABLE BIT(6)
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#define PW4_ENABLE BIT(8)
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#define PM0_ENABLE BIT(16)
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#define PM1_ENABLE BIT(18)
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_ENABLE 0x39
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#define DC_CMD_STATE_ACCESS 0x40
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#define READ_MUX (1 << 0)
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#define WRITE_MUX (1 << 2)
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#define READ_MUX BIT(0)
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#define WRITE_MUX BIT(2)
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#define DC_CMD_STATE_CONTROL 0x41
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#define GENERAL_ACT_REQ (1 << 0)
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#define WIN_A_ACT_REQ (1 << 1)
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#define WIN_B_ACT_REQ (1 << 2)
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#define WIN_C_ACT_REQ (1 << 3)
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#define WIN_D_ACT_REQ (1 << 4)
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#define CURSOR_ACT_REQ (1 << 7)
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#define GENERAL_UPDATE (1 << 8)
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#define WIN_A_UPDATE (1 << 9)
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#define WIN_B_UPDATE (1 << 10)
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#define WIN_C_UPDATE (1 << 11)
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#define WIN_D_UPDATE (1 << 12)
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#define CURSOR_UPDATE (1 << 15)
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#define NC_HOST_TRIG (1 << 24)
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#define GENERAL_ACT_REQ BIT(0)
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#define WIN_A_ACT_REQ BIT(1)
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#define WIN_B_ACT_REQ BIT(2)
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#define WIN_C_ACT_REQ BIT(3)
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#define WIN_D_ACT_REQ BIT(4)
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#define CURSOR_ACT_REQ BIT(7)
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#define GENERAL_UPDATE BIT(8)
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#define WIN_A_UPDATE BIT(9)
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#define WIN_B_UPDATE BIT(10)
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#define WIN_C_UPDATE BIT(11)
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#define WIN_D_UPDATE BIT(12)
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#define CURSOR_UPDATE BIT(15)
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#define NC_HOST_TRIG BIT(24)
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#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
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#define WINDOW_A_SELECT (1 << 4)
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#define WINDOW_B_SELECT (1 << 5)
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#define WINDOW_C_SELECT (1 << 6)
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#define WINDOW_D_SELECT (1 << 7)
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#define WINDOW_A_SELECT BIT(4)
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#define WINDOW_B_SELECT BIT(5)
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#define WINDOW_C_SELECT BIT(6)
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#define WINDOW_D_SELECT BIT(7)
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#define DC_CMD_REG_ACT_CONTROL 0x043
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@@ -125,12 +125,13 @@
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// DC_DISP shadowed registers.
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DSI_ENABLE (1 << 29)
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#define SOR1_TIMING_CYA (1 << 27)
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#define SOR1_ENABLE (1 << 26)
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#define SOR_ENABLE (1 << 25)
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#define CURSOR_ENABLE (1 << 16)
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#define CURSOR_ENABLE BIT(16)
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#define SOR_ENABLE BIT(25)
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#define SOR1_ENABLE BIT(26)
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#define SOR1_TIMING_CYA BIT(27)
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#define DSI_ENABLE BIT(29)
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#define HDMI_ENABLE BIT(30)
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
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@@ -142,6 +143,7 @@
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#define DC_DISP_FRONT_PORCH 0x40A
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#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
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#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
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#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
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@@ -155,7 +157,6 @@
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#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
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#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
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#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
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#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
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@@ -189,8 +190,8 @@
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#define BASE_COLOR_SIZE_888 (8 << 0)
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#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
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#define SC1_H_QUALIFIER_NONE (1 << 16)
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#define SC0_H_QUALIFIER_NONE (1 << 0)
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#define SC0_H_QUALIFIER_NONE BIT(0)
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#define SC1_H_QUALIFIER_NONE BIT(16)
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#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
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#define DE_SELECT_ACTIVE_BLANK (0 << 0)
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@@ -217,6 +218,7 @@
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#define CURSOR_SIZE_128 (2 << 24)
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#define CURSOR_SIZE_256 (3 << 24)
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#define DC_DISP_CURSOR_POSITION 0x440
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#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
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#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
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#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
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#define CURSOR_BLEND_2BIT (0 << 24)
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@@ -247,12 +249,12 @@
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// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
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#define DC_WIN_WIN_OPTIONS 0x700
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#define H_DIRECTION (1 << 0)
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#define V_DIRECTION (1 << 2)
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#define SCAN_COLUMN (1 << 4)
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#define COLOR_EXPAND (1 << 6)
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#define CSC_ENABLE (1 << 18)
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#define WIN_ENABLE (1 << 30)
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#define H_DIRECTION BIT(0)
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#define V_DIRECTION BIT(2)
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#define SCAN_COLUMN BIT(4)
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#define COLOR_EXPAND BIT(6)
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#define CSC_ENABLE BIT(18)
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#define WIN_ENABLE BIT(30)
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#define DC_WIN_BUFFER_CONTROL 0x702
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#define BUFFER_CONTROL_HOST 0
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@@ -369,36 +371,36 @@
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#define DSI_INT_MASK 0xE
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#define DSI_HOST_CONTROL 0xF
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#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
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#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
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#define DSI_HOST_CONTROL_ECC BIT(0)
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#define DSI_HOST_CONTROL_CS BIT(1)
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#define DSI_HOST_CONTROL_PKT_BTA BIT(2)
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#define DSI_HOST_CONTROL_IMM_BTA BIT(3)
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#define DSI_HOST_CONTROL_FIFO_SEL BIT(4)
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#define DSI_HOST_CONTROL_HS BIT(5)
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#define DSI_HOST_CONTROL_RAW BIT(6)
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#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
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#define DSI_HOST_CONTROL_RAW (1 << 6)
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#define DSI_HOST_CONTROL_HS (1 << 5)
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#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
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#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
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#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
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#define DSI_HOST_CONTROL_CS (1 << 1)
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#define DSI_HOST_CONTROL_ECC (1 << 0)
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#define DSI_HOST_CONTROL_CRC_RESET BIT(20)
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#define DSI_HOST_CONTROL_FIFO_RESET BIT(21)
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#define DSI_CONTROL 0x10
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#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
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#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
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#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
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#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
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#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
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#define DSI_CONTROL_DCS_ENABLE (1 << 3)
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#define DSI_CONTROL_HOST_ENABLE BIT(0)
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#define DSI_CONTROL_VIDEO_ENABLE BIT(1)
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#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
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#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
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#define DSI_CONTROL_HOST_ENABLE (1 << 0)
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#define DSI_CONTROL_DCS_ENABLE BIT(3)
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#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
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#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
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#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
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#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
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#define DSI_CONTROL_HS_CLK_CTRL BIT(20)
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#define DSI_SOL_DELAY 0x11
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#define DSI_MAX_THRESHOLD 0x12
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#define DSI_TRIGGER 0x13
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#define DSI_TRIGGER_HOST (1 << 1)
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#define DSI_TRIGGER_VIDEO (1 << 0)
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#define DSI_TRIGGER_VIDEO BIT(0)
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#define DSI_TRIGGER_HOST BIT(1)
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#define DSI_TX_CRC 0x14
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#define DSI_STATUS 0x15
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@@ -430,20 +432,20 @@
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#define DSI_BTA_TIMING 0x3F
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#define DSI_TIMEOUT_0 0x44
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#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
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#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_1 0x45
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#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
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#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
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#define DSI_TO_TALLY 0x46
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#define DSI_PAD_CONTROL_0 0x4B
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#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
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#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK BIT(8)
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#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
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#define DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24)
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#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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@@ -453,10 +455,10 @@
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#define DSI_PAD_CONTROL_2 0x50
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#define DSI_PAD_CONTROL_3 0x51
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#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
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#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
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#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
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#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
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#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
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#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
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#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
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#define DSI_PAD_CONTROL_4 0x52
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#define DSI_INIT_SEQ_DATA_15 0x5F
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@@ -493,6 +495,7 @@
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#define MIPI_DCS_GET_DISPLAY_ID 0x04
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#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
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#define MIPI_DCS_EXIT_SLEEP_MODE 0x11
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#define MIPI_DCS_SET_DISPLAY_OFF 0x28
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#define MIPI_DCS_SET_DISPLAY_ON 0x29
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/* Switch Panels:
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