tsec: Don't disable HOST1x clock because it's used
Tsec keys function always disabled host1x clock after running.
This interferes with display interface and disables further window frame syncing.
Display_end code already handles disable and reset of said clock.
It also fixes an ancient bug that was mitigated by removing the 5 frame sync on HOST1X_SYNC_SYNCPT_9 at channel 0:
5fd9daa364 (diff-6b0c56eab8515465d559ff0ea73a22c3L152)
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@@ -69,15 +69,16 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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bpmp_mmu_disable();
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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//Enable clocks.
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// Enable clocks.
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clock_enable_host1x();
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usleep(2);
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clock_enable_tsec();
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clock_enable_sor_safe();
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clock_enable_sor0();
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clock_enable_sor1();
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clock_enable_kfuse();
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//Configure Falcon.
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// Configure Falcon.
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TSEC(TSEC_DMACTL) = 0;
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TSEC(TSEC_IRQMSET) =
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TSEC_IRQMSET_EXT(0xFF) |
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@@ -99,7 +100,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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goto out;
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}
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//Load firmware or emulate memio environment for newer TSEC fw.
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// Load firmware or emulate memio environment for newer TSEC fw.
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if (kb == KB_FIRMWARE_VERSION_620)
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TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8;
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else
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@@ -174,8 +175,8 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE);
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}
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//Execute firmware.
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HOST1X(0x3300) = 0x34C2E1DA;
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// Execute firmware.
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTVEC) = 0;
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@@ -251,8 +252,8 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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goto out_free;
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}
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//Fetch result.
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HOST1X(0x3300) = 0;
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// Fetch result.
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0;
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u32 buf[4];
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buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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@@ -271,13 +272,12 @@ out_free:;
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out:;
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//Disable clocks.
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// Disable clocks.
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clock_disable_kfuse();
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clock_disable_sor1();
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clock_disable_sor0();
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clock_disable_sor_safe();
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clock_disable_tsec();
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clock_disable_host1x();
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bpmp_mmu_enable();
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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