bdk: small refactor
This commit is contained in:
CTCaer
@@ -90,7 +90,7 @@ enum
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FUSE_NX_HW_TYPE_ICOSA,
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FUSE_NX_HW_TYPE_IOWA,
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FUSE_NX_HW_TYPE_HOAG,
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FUSE_NX_HW_TYPE_AULA
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FUSE_NX_HW_TYPE_AULA
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};
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enum
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@@ -141,7 +141,7 @@ static void _config_gpios(bool nx_hoag)
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static void _config_pmc_scratch()
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{
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset WDT_DURING_BR.
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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}
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@@ -259,7 +259,7 @@ static void _config_se_brom()
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// se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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// This memset needs to happen here, else TZRAM will behave weirdly later on.
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memset((void *)TZRAM_BASE, 0, SZ_64K);
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memset((void *)TZRAM_BASE, 0, TZRAM_SIZE);
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PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
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SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.
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@@ -126,6 +126,8 @@
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#define PINMUX_DRIVE_3X (2 << 13)
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#define PINMUX_DRIVE_4X (3 << 13)
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#define PINMUX_PREEMP BIT(15)
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void pinmux_config_uart(u32 idx);
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void pinmux_config_i2c(u32 idx);
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@@ -40,23 +40,24 @@
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#define APBDEV_PMC_PWRGATE_STATUS 0x38
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#define APBDEV_PMC_NO_IOPOWER 0x44
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#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
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#define PMC_NO_IOPOWER_SDMMC4_IO_EN BIT(14)
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#define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
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#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_SCRATCH0 0x50
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#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
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#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
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#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_FASTBOOT | \
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#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_BOOTLOADER | \
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PMC_SCRATCH0_MODE_PAYLOAD)
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#define APBDEV_PMC_BLINK_TIMER 0x40
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#define APBDEV_PMC_BLINK_TIMER 0x40
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#define PMC_BLINK_ON(n) ((n & 0x7FFF))
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#define PMC_BLINK_FORCE BIT(15)
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#define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16)
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#define APBDEV_PMC_SCRATCH1 0x54
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#define APBDEV_PMC_SCRATCH20 0xA0
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#define APBDEV_PMC_SCRATCH20 0xA0 // ODM data/config scratch.
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#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
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#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
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#define APBDEV_PMC_PWR_DET_VAL 0xE4
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@@ -68,9 +69,13 @@
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#define APBDEV_PMC_CRYPTO_OP 0xF4
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#define PMC_CRYPTO_OP_SE_ENABLE 0
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#define PMC_CRYPTO_OP_SE_DISABLE 1
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#define APBDEV_PMC_PLLP_WB0_OVERRIDE 0xF8
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#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE BIT(11)
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#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
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#define APBDEV_PMC_SCRATCH33 0x120
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#define APBDEV_PMC_SCRATCH37 0x130
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#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN"
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#define APBDEV_PMC_SCRATCH39 0x138
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#define APBDEV_PMC_SCRATCH40 0x13C
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22)
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@@ -103,14 +108,23 @@
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#define APBDEV_PMC_SCRATCH45 0x234
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#define APBDEV_PMC_SCRATCH46 0x238
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#define APBDEV_PMC_SCRATCH49 0x244
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#define APBDEV_PMC_SCRATCH52 0x250
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#define APBDEV_PMC_SCRATCH53 0x254
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#define APBDEV_PMC_SCRATCH54 0x258
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#define APBDEV_PMC_SCRATCH55 0x25C
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#define APBDEV_PMC_TSC_MULT 0x2B4
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#define APBDEV_PMC_STICKY_BITS 0x2C0
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#define PMC_STICKY_BITS_HDA_LPBK_DIS BIT(0)
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#define APBDEV_PMC_SEC_DISABLE2 0x2C4
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#define APBDEV_PMC_WEAK_BIAS 0x2C8
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#define APBDEV_PMC_REG_SHORT 0x2CC
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#define APBDEV_PMC_SEC_DISABLE3 0x2D8
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#define APBDEV_PMC_SECURE_SCRATCH21 0x334
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#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4)
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#define APBDEV_PMC_SECURE_SCRATCH22 0x338 // AArch32 reset address.
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#define APBDEV_PMC_SECURE_SCRATCH32 0x360
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#define APBDEV_PMC_SECURE_SCRATCH34 0x368 // AArch64 reset address.
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#define APBDEV_PMC_SECURE_SCRATCH35 0x36C // AArch64 reset hi-address.
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#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
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#define APBDEV_PMC_CNTRL2 0x440
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#define PMC_CNTRL2_WAKE_INT_EN BIT(0)
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@@ -133,11 +147,25 @@
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_SCRATCH201 0x844
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#define APBDEV_PMC_SCRATCH250 0x908
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#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
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#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
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#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
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#define APBDEV_PMC_SECURE_SCRATCH112 0xB18
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#define APBDEV_PMC_SECURE_SCRATCH113 0xB1C
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#define APBDEV_PMC_SECURE_SCRATCH119 0xB34
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// Only in T210B01.
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE0 0xA48
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE1 0xA4C
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE2 0xA50
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE3 0xA54
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE4 0xA58
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE5 0xA5C
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE6 0xA60
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE7 0xA64
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#define APBDEV_PMC_SCRATCH_WRITE_DISABLE8 0xA68
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#define APBDEV_PMC_LED_BREATHING_CTRL 0xB48
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#define PMC_LED_BREATHING_CTRL_ENABLE BIT(0)
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#define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1)
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202
bdk/soc/t210.h
202
bdk/soc/t210.h
@@ -27,8 +27,10 @@
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#define DISPLAY_A_BASE 0x54200000
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#define DSI_BASE 0x54300000
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#define VIC_BASE 0x54340000
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#define NVDEC_BASE 0x54480000
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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#define MSELECT_BASE 0x50060000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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@@ -71,6 +73,8 @@
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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#define TZRAM_BASE 0x7C010000
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#define TZRAM_SIZE 0x10000
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#define TZRAM_T210B01_SIZE 0x3C000
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#define USB_BASE 0x7D000000
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#define USB_OTG_BASE USB_BASE
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#define USB1_BASE 0x7D004000
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@@ -82,8 +86,10 @@
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#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
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#define DSI(off) _REG(DSI_BASE, off)
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#define VIC(off) _REG(VIC_BASE, off)
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#define NVDEC(off) _REG(NVDEC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define MSELECT(off) _REG(MSELECT_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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@@ -130,91 +136,91 @@
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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#define HOST1X_CH0_SYNC_BASE 0x2100
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#define HOST1X_CH0_SYNC_BASE 0x2100
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#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4)
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#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
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/*! EVP registers. */
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#define EVP_CPU_RESET_VECTOR 0x100
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#define EVP_COP_RESET_VECTOR 0x200
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#define EVP_COP_UNDEF_VECTOR 0x204
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#define EVP_COP_SWI_VECTOR 0x208
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#define EVP_CPU_RESET_VECTOR 0x100
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#define EVP_COP_RESET_VECTOR 0x200
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#define EVP_COP_UNDEF_VECTOR 0x204
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#define EVP_COP_SWI_VECTOR 0x208
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#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
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#define EVP_COP_DATA_ABORT_VECTOR 0x210
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define EVP_COP_IRQ_STS 0x220
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#define EVP_COP_DATA_ABORT_VECTOR 0x210
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define EVP_COP_IRQ_STS 0x220
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/*! Primary Interrupt Controller registers. */
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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#define PRI_ICTLR_CPU_IER 0x20
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#define PRI_ICTLR_CPU_IER_SET 0x24
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#define PRI_ICTLR_CPU_IER_CLR 0x28
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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#define PRI_ICTLR_CPU_IER 0x20
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#define PRI_ICTLR_CPU_IER_SET 0x24
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#define PRI_ICTLR_CPU_IER_CLR 0x28
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#define PRI_ICTLR_CPU_IEP_CLASS 0x2C
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#define PRI_ICTLR_COP_IER 0x30
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#define PRI_ICTLR_COP_IER_SET 0x34
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IER 0x30
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#define PRI_ICTLR_COP_IER_SET 0x34
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IEP_CLASS 0x3C
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
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#define PRIORITY_SELECT_USB BIT(6) // USB-OTG.
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#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
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#define PRIORITY_SELECT_USB3 BIT(17) // XUSB.
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
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#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7)
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#define AHB_MEM_IMMEDIATE BIT(18)
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#define AHB_GIZMO_APB_DMA 0x14
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_SDMMC4 0x48
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#define AHB_GIZMO_USB2 0x7C
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#define AHB_GIZMO_USB3 0x80
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#define AHB_GIZMO_IMMEDIATE BIT(18)
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
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#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
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#define MST_ID(x) (((x) & 0x1F) << 26)
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#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
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#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG.
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#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
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#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
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#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
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#define MEM_PREFETCH_ENABLE BIT(31)
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
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#define PRIORITY_SELECT_USB BIT(6) // USB-OTG.
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#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
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#define PRIORITY_SELECT_USB3 BIT(17) // XUSB.
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
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#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7)
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#define AHB_MEM_IMMEDIATE BIT(18)
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#define AHB_GIZMO_APB_DMA 0x14
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_SDMMC4 0x48
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#define AHB_GIZMO_USB2 0x7C
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#define AHB_GIZMO_USB3 0x80
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#define AHB_GIZMO_IMMEDIATE BIT(18)
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
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#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
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#define MST_ID(x) (((x) & 0x1F) << 26)
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#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
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#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG.
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#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
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#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
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#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
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#define MEM_PREFETCH_ENABLE BIT(31)
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#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC
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#define MEM_WRQUE_SE_MST_ID BIT(14)
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#define AHB_AHB_SPARE_REG 0x110
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#define MEM_WRQUE_SE_MST_ID BIT(14)
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#define AHB_AHB_SPARE_REG 0x110
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_HIDREV 0x804
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#define GP_HIDREV_MAJOR_T210 0x1
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#define GP_HIDREV_MAJOR_T210B01 0x2
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#define APB_MISC_GP_ASDBGREG 0x810
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_PP_STRAPPING_OPT_A 0x8
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_HIDREV 0x804
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#define GP_HIDREV_MAJOR_T210 0x1
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#define GP_HIDREV_MAJOR_T210B01 0x2
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#define APB_MISC_GP_ASDBGREG 0x810
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
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#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
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/*! Secure boot registers. */
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1)
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#define SB_CSR_PIROM_DISABLE BIT(4)
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#define SB_AA64_RESET_LOW 0x30
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#define SB_AA64_RST_AARCH64_MODE_EN BIT(0)
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#define SB_AA64_RESET_HIGH 0x34
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#define SB_CSR 0x0
|
||||
#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1)
|
||||
#define SB_CSR_PIROM_DISABLE BIT(4)
|
||||
#define SB_AA64_RESET_LOW 0x30
|
||||
#define SB_AA64_RST_AARCH64_MODE_EN BIT(0)
|
||||
#define SB_AA64_RESET_HIGH 0x34
|
||||
|
||||
/*! SOR registers. */
|
||||
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8
|
||||
@@ -231,7 +237,7 @@
|
||||
#define SYSCTR0_CNTCR 0x00
|
||||
#define SYSCTR0_CNTFID0 0x20
|
||||
#define SYSCTR0_COUNTERS_BASE 0xFD0
|
||||
#define SYSCTR0_COUNTERS 12
|
||||
#define SYSCTR0_COUNTERS 12
|
||||
#define SYSCTR0_COUNTERID0 0xFE0
|
||||
#define SYSCTR0_COUNTERID1 0xFE4
|
||||
#define SYSCTR0_COUNTERID2 0xFE8
|
||||
@@ -269,28 +275,42 @@
|
||||
#define EMC_HEKA_UPD BIT(30)
|
||||
|
||||
/*! Flow controller registers. */
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
|
||||
#define HALT_COP_GIC_IRQ BIT(9)
|
||||
#define HALT_COP_LIC_IRQ BIT(11)
|
||||
#define HALT_COP_SEC BIT(23)
|
||||
#define HALT_COP_MSEC BIT(24)
|
||||
#define HALT_COP_USEC BIT(25)
|
||||
#define HALT_COP_JTAG BIT(28)
|
||||
#define HALT_COP_WAIT_EVENT BIT(30)
|
||||
#define HALT_COP_STOP_UNTIL_IRQ BIT(31)
|
||||
#define HALT_COP_MAX_CNT 0xFF
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
|
||||
#define FLOW_CTLR_CPU0_CSR 0x8
|
||||
#define FLOW_CTLR_CPU1_CSR 0x18
|
||||
#define FLOW_CTLR_CPU2_CSR 0x20
|
||||
#define FLOW_CTLR_CPU3_CSR 0x28
|
||||
#define FLOW_CTLR_RAM_REPAIR 0x40
|
||||
#define RAM_REPAIR_REQ BIT(0)
|
||||
#define RAM_REPAIR_STS BIT(1)
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
|
||||
#define HALT_COP_GIC_IRQ BIT(9)
|
||||
#define HALT_COP_LIC_IRQ BIT(11)
|
||||
#define HALT_COP_SEC BIT(23)
|
||||
#define HALT_COP_MSEC BIT(24)
|
||||
#define HALT_COP_USEC BIT(25)
|
||||
#define HALT_COP_JTAG BIT(28)
|
||||
#define HALT_COP_WAIT_EVENT BIT(30)
|
||||
#define HALT_COP_STOP_UNTIL_IRQ BIT(31)
|
||||
#define HALT_COP_MAX_CNT 0xFF
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
|
||||
#define FLOW_CTLR_CPU0_CSR 0x8
|
||||
#define FLOW_CTLR_CPU1_CSR 0x18
|
||||
#define FLOW_CTLR_CPU2_CSR 0x20
|
||||
#define FLOW_CTLR_CPU3_CSR 0x28
|
||||
#define FLOW_CTLR_RAM_REPAIR 0x40
|
||||
#define RAM_REPAIR_REQ BIT(0)
|
||||
#define RAM_REPAIR_STS BIT(1)
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
|
||||
#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0)
|
||||
#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0)
|
||||
|
||||
/* MSelect registers */
|
||||
#define MSELECT_CONFIG 0x00
|
||||
#define MSELECT_CFG_ERR_RESP_EN_PCIE BIT(24)
|
||||
#define MSELECT_CFG_ERR_RESP_EN_GPU BIT(25)
|
||||
#define MSELECT_CFG_WRAP_TO_INCR_BPMP BIT(27)
|
||||
#define MSELECT_CFG_WRAP_TO_INCR_PCIE BIT(28)
|
||||
#define MSELECT_CFG_WRAP_TO_INCR_GPU BIT(29)
|
||||
|
||||
/* NVDEC registers */
|
||||
#define NVDEC_SA_KEYSLOT_FALCON 0x2100
|
||||
#define NVDEC_SA_KEYSLOT_TZ 0x2104
|
||||
#define NVDEC_SA_KEYSLOT_OTF 0x210C
|
||||
#define NVDEC_SA_KEYSLOT_GLOBAL_RW 0x2118
|
||||
#define NVDEC_VPR_ALL_OTF_GOTO_VPR 0x211C
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user