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Add 4/5.X and 6.X hw config changes

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Thanks to @balika011 for notice on 2.x vs 5.x changes.

(Some 2.x vs 5.x changes were added with the `fdd94ff` commit)
This commit is contained in:
Kostas Missos
2018-09-19 00:11:18 +03:00
parent b9e348fc17
commit 7aeac2c379
8 changed files with 40 additions and 13 deletions
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10
bootloader/soc/cluster.c
View File

@@ -27,11 +27,13 @@ void _cluster_enable_power()
{
u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO);
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & 0xDF);
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 0x09);
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
// Enable cores power.
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_NFSR_ENABLE);
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL);
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); // 1-3.x: MAX77621_NFSR_ENABLE
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); // 1-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37);
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37);
}
@@ -103,7 +105,7 @@ void cluster_boot_cpu0(u32 entry)
// Enable cluster 0 non-CPU.
_cluster_pmc_enable_partition(0x8000, 15, true);
// Enable CE0.
_cluster_pmc_enable_partition(0x4000, 14);
_cluster_pmc_enable_partition(0x4000, 14, true);
// Request and wait for RAM repair.
FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;

8
bootloader/soc/cluster.h
View File

@@ -20,7 +20,15 @@
#include "../utils/types.h"
/*! Flow controller registers. */
#define LOW_CTLR_HALT_CPU0_EVENTS 0x0
#define LOW_CTLR_HALT_CPU1_EVENTS 0x14
#define LOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define LOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98

11
bootloader/soc/i2c.c
View File

@@ -61,7 +61,7 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
{
if (size > 4)
if (size > 8)
return 0;
vu32 *base = (vu32 *)i2c_addrs[idx];
@@ -77,7 +77,14 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
return 0;
u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
memcpy(buf, &tmp, size);
if (size > 4)
{
memcpy(buf, &tmp, 4);
tmp = base[I2C_CMD_DATA2]; // Get MS value.
memcpy(buf + 4, &tmp, size - 4);
}
else
memcpy(buf, &tmp, size);
return 1;
}

1
bootloader/soc/t210.h
View File

@@ -101,6 +101,7 @@
#define TEST_REG(off) _REG(0x0, off)
/*! Misc registers. */
#define APB_MISC_PP_STRAPPING_OPT_A 0x08
#define APB_MISC_PP_PINMUX_GLOBAL 0x40
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64