Add more register names + refactoring
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@@ -122,7 +122,7 @@ static void _se_lock(bool lock_se)
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}
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memset((void *)IPATCH_BASE, 0, 14 * sizeof(u32));
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SB(SB_CSR) = 0x10; // Protected IROM enable.
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SB(SB_CSR) = SB_CSR_PIROM_DISABLE;
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// This is useful for documenting the bits in the SE config registers, so we can keep it around.
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/*gfx_printf("SE(SE_SECURITY_0) = %08X\n", SE(SE_SECURITY_0));
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@@ -167,7 +167,6 @@ void _pmc_scratch_lock(u32 kb)
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void _sysctr0_reset()
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{
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000;
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SYSCTR0(SYSCTR0_CNTCR) = 0;
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SYSCTR0(SYSCTR0_COUNTERID0) = 0;
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SYSCTR0(SYSCTR0_COUNTERID1) = 0;
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@@ -185,7 +184,7 @@ void _sysctr0_reset()
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int keygen(u8 *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, launch_ctxt_t *hos_ctxt)
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{
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u8 tmp[0x30];
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u8 tmp[0x20];
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u32 retries = 0;
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if (kb > KB_FIRMWARE_VERSION_MAX)
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@@ -729,7 +728,7 @@ int hos_launch(ini_sec_t *cfg)
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else
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cluster_boot_cpu0(ctxt.pkg1_id->secmon_base);
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while (!secmon_mb->out)
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usleep(1); // This only works when in IRAM or with a trained DRAM.
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; // A usleep(1) only works when in IRAM or with a trained DRAM.
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// Signal pkg2 ready and continue boot.
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secmon_mb->in = bootStatePkg2Continue;
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