bdk: whitespace refactor
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@@ -20,16 +20,17 @@
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#include "tsec.h"
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#include "tsec_t210.h"
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#include <memory_map.h>
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#include <mem/heap.h>
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#include <mem/mc.h>
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#include <mem/smmu.h>
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#include <sec/se_t210.h>
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#include <soc/bpmp.h>
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#include <soc/clock.h>
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#include <soc/kfuse.h>
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#include <soc/pmc.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <mem/heap.h>
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#include <mem/mc.h>
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#include <mem/smmu.h>
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#include <soc/timer.h>
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// #include <gfx_utils.h>
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@@ -57,9 +58,9 @@ static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offse
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else
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cmd = TSEC_DMATRFCMD_IMEM; // DMA IMEM (Instruction memmory)
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TSEC(TSEC_DMATRFMOFFS) = i_offset;
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TSEC(TSEC_DMATRFMOFFS) = i_offset;
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TSEC(TSEC_DMATRFFBOFFS) = pa_offset;
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TSEC(TSEC_DMATRFCMD) = cmd;
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TSEC(TSEC_DMATRFCMD) = cmd;
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return _tsec_dma_wait_idle();
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}
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@@ -83,7 +84,6 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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clock_enable_sor0();
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clock_enable_sor1();
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clock_enable_kfuse();
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kfuse_wait_ready();
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if (type == TSEC_FW_TYPE_NEW)
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@@ -102,16 +102,16 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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TSEC(TSEC_DMACTL) = 0;
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TSEC(TSEC_IRQMSET) =
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TSEC_IRQMSET_EXT(0xFF) |
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TSEC_IRQMSET_WDTMR |
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TSEC_IRQMSET_HALT |
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TSEC_IRQMSET_EXTERR |
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TSEC_IRQMSET_SWGEN0 |
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TSEC_IRQMSET_WDTMR |
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TSEC_IRQMSET_HALT |
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TSEC_IRQMSET_EXTERR |
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TSEC_IRQMSET_SWGEN0 |
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TSEC_IRQMSET_SWGEN1;
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TSEC(TSEC_IRQDEST) =
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TSEC_IRQDEST_EXT(0xFF) |
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TSEC_IRQDEST_HALT |
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TSEC_IRQDEST_EXTERR |
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TSEC_IRQDEST_SWGEN0 |
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TSEC_IRQDEST_HALT |
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TSEC_IRQDEST_EXTERR |
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TSEC_IRQDEST_SWGEN0 |
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TSEC_IRQDEST_SWGEN1;
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TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN;
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if (!_tsec_dma_wait_idle())
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@@ -128,6 +128,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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fwbuf = (u8 *)malloc(SZ_16K);
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u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100);
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memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size);
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TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8;
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}
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@@ -180,7 +181,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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mc = page_alloc(1);
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memcpy(mc, (void *)MC_BASE, SZ_PAGE);
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mc[MC_IRAM_BOM / 4] = 0;
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mc[MC_IRAM_TOM / 4] = 0x80000000;
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mc[MC_IRAM_TOM / 4] = DRAM_START;
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smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
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// IRAM
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@@ -197,10 +198,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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// Execute firmware.
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTVEC) = 0;
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TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU;
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TSEC(TSEC_BOOTVEC) = 0;
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TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU;
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if (type == TSEC_FW_TYPE_EMU)
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{
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@@ -279,10 +280,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB);
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buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB);
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SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
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SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
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memcpy(tsec_keys, &buf, SE_KEY_128_SIZE);
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}
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