Name more hardcoded values
This commit is contained in:
42
ipl/clock.h
42
ipl/clock.h
@@ -20,7 +20,9 @@
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#include "types.h"
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/*! Clock registers. */
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#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
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#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
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#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
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#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
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@@ -32,38 +34,78 @@
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
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#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
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#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
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#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
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#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
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#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
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#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
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#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
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#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
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#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
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#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
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#define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
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#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
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#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
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#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
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#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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/*! Generic clock descriptor. */
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typedef struct _clock_t
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