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Implement ms timer and fix all timers

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This will fix everything that uses a timer (or sleep).

Without this any function like eMMC/SD read/write/verify, TSEC/SE, etc can break when the time reaches the max value of the u32 microsecond timer (71minutes).

This fixes every possible breakage, including backup and restore (read/write/verify errors) that takes a lot of time.

The new max before a timer reset is now 48 days (the old one was 71 minutes)
This commit is contained in:
Kostas Missos
2018-07-04 18:39:26 +03:00
parent ebb9ca5bf5
commit 5e8eb1c57a
17 changed files with 146 additions and 129 deletions
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42
ipl/sdram.c
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@@ -42,27 +42,27 @@ static u32 _get_sdram_id()
static void _sdram_config(const sdram_params_t *params)
{
PMC(0x45C) = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF;
sleep(params->pmc_io_dpd3_req_wait);
usleep(params->pmc_io_dpd3_req_wait);
u32 req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000;
PMC(APBDEV_PMC_IO_DPD4_REQ) = (req >> 16 << 16) ^ 0x3FFF0000;
sleep(params->pmc_io_dpd4_req_wait);
usleep(params->pmc_io_dpd4_req_wait);
PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0xFFFF) & 0xC000FFFF;
sleep(params->pmc_io_dpd4_req_wait);
usleep(params->pmc_io_dpd4_req_wait);
PMC(APBDEV_PMC_WEAK_BIAS) = 0;
sleep(1);
usleep(1);
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
u32 wait_end = TMR(0x10) + 300;
u32 wait_end = get_tmr_us() + 300;
while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000))
{
if (TMR(0x10) >= wait_end)
if (get_tmr_us() >= wait_end)
goto break_nosleep;
}
sleep(10);
usleep(10);
break_nosleep:
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF);
@@ -77,7 +77,7 @@ break_nosleep:
EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1;
EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2;
EMC(EMC_TIMING_CONTROL) = 1;
sleep(1);
usleep(1);
EMC(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg;
if (params->emc_bct_spare2)
*(vu32 *)params->emc_bct_spare2 = params->emc_bct_spare3;
@@ -298,7 +298,7 @@ break_nosleep:
EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1;
EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval;
EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config;
sleep(params->emc_auto_cal_wait);
usleep(params->emc_auto_cal_wait);
if (params->emc_bct_spare8)
*(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9;
EMC(EMC_CFG_2) = params->emc_cfg2;
@@ -394,7 +394,7 @@ break_nosleep:
MC(MC_TIMING_CONTROL) = 1;
}
PMC(0x45C) = ((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000;
sleep(params->pmc_io_dpd3_req_wait);
usleep(params->pmc_io_dpd3_req_wait);
if (!params->emc_auto_cal_interval)
EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config | 0x200;
EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2;
@@ -409,29 +409,29 @@ break_nosleep:
}
}
EMC(EMC_TIMING_CONTROL) = 1;
sleep(params->emc_timing_control_wait);
usleep(params->emc_timing_control_wait);
PMC(0x4E4) &= 0xFFF8007F;
sleep(params->pmc_ddr_ctrl_wait);
usleep(params->pmc_ddr_ctrl_wait);
if (params->memory_type == 2)
{
EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
sleep(params->emc_pin_extra_wait + 200);
usleep(params->emc_pin_extra_wait + 200);
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256;
sleep(params->emc_pin_extra_wait + 500);
usleep(params->emc_pin_extra_wait + 500);
}
if (params->memory_type == 3)
{
EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
sleep(params->emc_pin_extra_wait + 200);
usleep(params->emc_pin_extra_wait + 200);
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256;
sleep(params->emc_pin_extra_wait + 2000);
usleep(params->emc_pin_extra_wait + 2000);
}
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101;
sleep(params->emc_pin_program_wait);
usleep(params->emc_pin_program_wait);
if (params->memory_type != 3)
EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1;
if (params->memory_type == 1)
sleep(params->emc_pin_extra_wait + 200);
usleep(params->emc_pin_extra_wait + 200);
if (params->memory_type == 3)
{
if (params->emc_bct_spare10)
@@ -449,12 +449,12 @@ break_nosleep:
if (params->emc_zcal_warm_cold_boot_enables & 1)
{
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0;
sleep(params->emc_zcal_init_wait);
usleep(params->emc_zcal_init_wait);
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3;
if (!(params->emc_dev_select & 2))
{
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1;
sleep(params->emc_zcal_init_wait);
usleep(params->emc_zcal_init_wait);
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3;
}
}
@@ -511,7 +511,7 @@ void sdram_init()
i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD1, 40); //40 = (1000 * 1100 - 600000) / 12500 -> 1.1V
PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
sleep(params->pmc_vddp_sel_wait);
usleep(params->pmc_vddp_sel_wait);
PMC(APBDEV_PMC_DDR_PWR) = PMC(APBDEV_PMC_DDR_PWR);
PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power;
PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short;