bdk: sdmmc: rename ddr100 to the actual HS100 name
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@@ -261,7 +261,7 @@
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#define SDHCI_TIMING_UHS_DDR50 12
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// SDR104 with a 163.2MHz -> 81.6MHz clock.
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#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
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#define SDHCI_TIMING_MMC_DDR100 14 // GC ASIC.
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#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC.
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/*! SDMMC Low power features. */
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#define SDMMC_POWER_SAVE_DISABLE 0
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