6.2.0 support
Co-Authored-By: nwert <nwert@users.noreply.github.com> Co-Authored-By: Balázs Triszka <balika011@gmail.com>
This commit is contained in:
Kostas Missos
171
bootloader/soc/smmu.c
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171
bootloader/soc/smmu.c
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 balika011
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "smmu.h"
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#include "../soc/cluster.h"
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#include "../soc/t210.h"
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#include "../mem/mc_t210.h"
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#include "../utils/util.h"
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#include "../utils/aarch64_util.h"
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bool smmu_used = false;
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u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
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//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
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u8 smmu_payload[] __attribute__((aligned(16))) = {
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0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
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0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
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0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
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0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
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0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
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0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
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0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0
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0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1]
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0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000
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0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0
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0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
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0x00, 0x00, 0x00, 0x00, // 0x2C:
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0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
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0x00, 0x00, 0x00, 0x00 // 0x34:
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};
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void *page_alloc(u32 num)
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{
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u8 *res = _pageheap;
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_pageheap += 0x1000 * num;
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memset(res, 0, 0x1000 * num);
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return res;
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}
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u32 *smmu_alloc_pdir()
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{
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u32 *pdir = (u32 *)page_alloc(1);
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for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn] = _PDE_VACANT(pdn);
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return pdir;
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}
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void smmu_flush_regs()
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{
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(void)MC(MC_SMMU_PTB_DATA);
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}
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void smmu_flush_all()
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{
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MC(MC_SMMU_PTC_FLUSH) = 0;
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smmu_flush_regs();
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MC(MC_SMMU_TLB_FLUSH) = 0;
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smmu_flush_regs();
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}
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void smmu_init(u32 secmon_base)
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{
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MC(MC_SMMU_PTB_ASID) = 0;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
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MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
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MC(MC_SMMU_PTC_FLUSH) = 0;
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MC(MC_SMMU_TLB_FLUSH) = 0;
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// Set the secmon address
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*(u32 *)(smmu_payload + 0x30) = secmon_base;
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}
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void smmu_enable()
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{
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if (smmu_used)
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return;
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cluster_boot_cpu0((u32)smmu_payload);
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smmu_used = true;
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msleep(100);
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smmu_flush_all();
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}
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bool smmu_is_used()
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{
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return smmu_used;
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}
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void smmu_exit()
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{
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*(uint32_t *)(smmu_payload + 0x14) = _NOP();
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}
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u32 *smmu_init_domain4(u32 dev_base, u32 asid)
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{
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u32 *pdir = smmu_alloc_pdir();
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
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smmu_flush_regs();
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MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
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smmu_flush_regs();
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return pdir;
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}
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u32 *smmu_get_pte(u32 *pdir, u32 iova)
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{
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u32 ptn = SMMU_ADDR_TO_PFN(iova);
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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u32 *ptbl;
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if (pdir[pdn] != _PDE_VACANT(pdn))
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ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
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else
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{
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ptbl = (u32 *)page_alloc(1);
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
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ptbl[pn] = _PTE_VACANT(addr);
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pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
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smmu_flush_all();
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}
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return &ptbl[ptn % SMMU_PTBL_COUNT];
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}
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
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{
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for (int i = 0; i < cnt; i++)
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{
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u32 *pte = smmu_get_pte(pdir, addr);
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*pte = SMMU_ADDR_TO_PFN(page) | attr;
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addr += 0x1000;
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page += 0x1000;
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}
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smmu_flush_all();
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}
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u32 *smmu_init_for_tsec()
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{
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return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
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}
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void smmu_deinit_for_tsec()
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{
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MC(MC_SMMU_PTB_ASID) = 1;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TSEC_ASID) = 0;
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smmu_flush_regs();
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}
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82
bootloader/soc/smmu.h
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82
bootloader/soc/smmu.h
Normal file
@@ -0,0 +1,82 @@
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "../utils/types.h"
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#define SMMU_HEAP_ADDR 0xA0000000
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_ERR_STATUS 0x8
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#define MC_ERR_ADR 0xc
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#define MC_SMMU_CONFIG 0x10
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#define MC_SMMU_TLB_CONFIG 0x14
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#define MC_SMMU_PTC_CONFIG 0x18
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#define MC_SMMU_PTB_ASID 0x1c
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_TSEC_ASID 0x294
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#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
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#define SMMU_PDE_NEXT_SHIFT 28
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#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
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#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30
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#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000FFFFF
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
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#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
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#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
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#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
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#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
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#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
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void *page_alloc(u32 num);
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u32 *smmu_alloc_pdir();
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void smmu_flush_regs();
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void smmu_flush_all();
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void smmu_init(u32 secmon_base);
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void smmu_enable();
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bool smmu_is_used();
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void smmu_exit();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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u32 *smmu_init_for_tsec();
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void smmu_deinit_for_tsec();
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@@ -119,6 +119,12 @@
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#define SB_AA64_RESET_LOW 0x30
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#define SB_AA64_RESET_HIGH 0x34
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/*! SOR registers. */
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#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB 0x208
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB 0x20C
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/*! RTC registers. */
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#define APBDEV_RTC_SECONDS 0x8
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#define APBDEV_RTC_SHADOW_SECONDS 0xC
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@@ -126,6 +132,19 @@
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/*! SYSCTR0 registers. */
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#define SYSCTR0_CNTFID0 0x20
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#define SYSCTR0_CNTCR 0x00
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#define SYSCTR0_COUNTERID0 0xFE0
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#define SYSCTR0_COUNTERID1 0xFE4
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#define SYSCTR0_COUNTERID2 0xFE8
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#define SYSCTR0_COUNTERID3 0xFEC
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#define SYSCTR0_COUNTERID4 0xFD0
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#define SYSCTR0_COUNTERID5 0xFD4
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#define SYSCTR0_COUNTERID6 0xFD8
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#define SYSCTR0_COUNTERID7 0xFDC
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#define SYSCTR0_COUNTERID8 0xFF0
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#define SYSCTR0_COUNTERID9 0xFF4
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#define SYSCTR0_COUNTERID10 0xFF8
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#define SYSCTR0_COUNTERID11 0xFFC
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/*! TMR registers. */
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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