Fix HDCP + some bugfixes
Thanks @hexkyz for taking the time to recheck for the missing 6.x changes
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@@ -41,7 +41,7 @@ static u32 _get_sdram_id()
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static void _sdram_config(const sdram_params_t *params)
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{
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PMC(0x45C) = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF;
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PMC(APBDEV_PMC_IO_DPD3_REQ) = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF;
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usleep(params->pmc_io_dpd3_req_wait);
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u32 req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000;
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@@ -393,7 +393,7 @@ break_nosleep:
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*(vu32 *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data;
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MC(MC_TIMING_CONTROL) = 1;
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}
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PMC(0x45C) = ((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000;
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PMC(APBDEV_PMC_IO_DPD3_REQ) = ((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000;
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usleep(params->pmc_io_dpd3_req_wait);
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if (!params->emc_auto_cal_interval)
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EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config | 0x200;
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@@ -410,7 +410,7 @@ break_nosleep:
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}
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EMC(EMC_TIMING_CONTROL) = 1;
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usleep(params->emc_timing_control_wait);
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PMC(0x4E4) &= 0xFFF8007F;
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PMC(APBDEV_PMC_DDR_CNTRL) &= 0xFFF8007F;
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usleep(params->pmc_ddr_ctrl_wait);
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if (params->memory_type == 2)
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{
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@@ -459,7 +459,7 @@ break_nosleep:
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}
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}
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}
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PMC(0x1D0) = params->pmc_ddr_cfg;
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PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg;
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if (params->memory_type - 1 <= 2)
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{
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EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval;
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@@ -486,7 +486,7 @@ break_nosleep:
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MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access;
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MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access;
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MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;
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MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; //Disable write access to a bunch of MC registers.
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MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; //Disable write access to a bunch of EMC registers.
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}
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const void *sdram_get_params()
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