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bdk: sdmmc: timing changes

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- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
This commit is contained in:
CTCaer
2022-10-11 04:05:12 +03:00
parent eaa25114ad
commit 197ce4c76f
5 changed files with 33 additions and 29 deletions
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7
bdk/storage/sdmmc_driver.h
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@@ -206,9 +206,10 @@
#define SDHCI_TIMING_UHS_SDR25 9
#define SDHCI_TIMING_UHS_SDR50 10
#define SDHCI_TIMING_UHS_SDR104 11
#define SDHCI_TIMING_UHS_SDR82 12 // SDR104 with a 163.2MHz -> 81.6MHz clock.
#define SDHCI_TIMING_UHS_DDR50 13
#define SDHCI_TIMING_MMC_HS102 14
#define SDHCI_TIMING_UHS_DDR50 12
// SDR104 with a 163.2MHz -> 81.6MHz clock.
#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
#define SDHCI_TIMING_MMC_DDR100 14 // GC ASIC.
#define SDHCI_CAN_64BIT BIT(28)