Files

CTCaer b6ec6a8f6e minerva: update tov1.6_T210/v0.1_T21X

T21X v0.1:
- Add IRB/no table support
T210 v1.6/Common:
- Add a proper table for 8GB T210 config instead of editing a 4GB one
- Increase timeout to 2ms
- Generally improve checks and guard against unknown SoCs/SKUs
- Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs

2025-12-17 05:58:09 +02:00

Makefile

minerva: update tov1.6_T210/v0.1_T21X

2025-12-17 05:58:09 +02:00

mtc_mc_emc_regs.h

minerva: update tov1.6_T210/v0.1_T21X

2025-12-17 05:58:09 +02:00

mtc_switch_tables.h

minerva: update tov1.6_T210/v0.1_T21X

2025-12-17 05:58:09 +02:00

mtc_table.h

lib: minerva: refactor table

2023-06-08 04:49:16 +03:00

mtc.h

minerva: update tov1.6_T210/v0.1_T21X

2025-12-17 05:58:09 +02:00

README.md

refactor: Remove all unwanted whitespace

2019-10-18 18:02:06 +03:00

sys_sdrammtc.c

minerva: update tov1.6_T210/v0.1_T21X

2025-12-17 05:58:09 +02:00

types.h

minerva: make is_pllmb and fsp automatic

2022-01-16 01:43:16 +02:00

README.md

Minerva Training Cell

Custom Nvidia Tegra X1 DRAM trainer.

For more, check Here.

Minerva Training Cell (c) 2018 CTCaer.

/* Pain... And suffering. */