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ef1ce85735ea2f58eb15e8558a0010af65d1a052
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65 Commits

Author SHA1 Message Date
CTCaer
ef1ce85735 bdk: sdmmc: rename bkops define 
And remove dead code.
 2026-03-18 22:35:01 +02:00
CTCaer
25fda88e46 bdk: sdmmc: homogenize return values 
The actual target of this refactoring.
 2026-02-22 08:32:34 +02:00
CTCaer
e6984a149b bdk: sdmmc: remove dependency to ram for init 2026-02-12 21:53:59 +02:00
CTCaer
9171fa70c9 bdk: mem: rename sdmmc dma buffer 2026-02-12 21:38:56 +02:00
CTCaer
4797b42e76 bdk: sdmmc: add defines for max block number 2025-12-17 04:30:12 +02:00
CTCaer
bdf556fd36 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2025-08-27 15:08:11 +03:00
CTCaer
b3194f6379 bdk: mc: fix warning for arbiter check 2025-04-30 09:14:32 +03:00
CTCaer
b9496f81b1 bdk: sdmmc: add extention regs read/parse 2025-01-24 16:42:14 +02:00
CTCaer
595ac2c11e bdk: sdmmc: refactor error checking on rw 
And also check if card status is ok after a read/write.
 2025-01-24 15:44:33 +02:00
CTCaer
dcd4e4c4ec bdk: sdmmc: check that cmd timed out if SDSC 
Instead of assuming that, check it.
This fix will make SDUC not to be assumed as SDSC.
 2025-01-24 15:40:38 +02:00
CTCaer
018ed3f38a bdk: sdmmc: update unstuff_bits to use mod 
Since unstuff_bits only supports 128bits, instead of subtracting the correct amount of bits with the offset array, use % 128.
 2025-01-24 15:39:17 +02:00
CTCaer
e030a4ad6d bdk: sdmmc: small refactor 2025-01-24 15:30:10 +02:00
CTCaer
5ce22a67dc bdk: sdmmc: check for out bounds access 2025-01-24 15:21:20 +02:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
75a4a8ba1d bdk: sdmmc: remove higher power limits 
UHS-I Cards force a max of 1.44W even if higher modes are selected.
This does not change functionality, so remove them as unused.
 2024-06-10 13:37:28 +03:00
CTCaer
a37b5c7841 bdk: sdmmc: no need to raise power limit for HS25 2024-06-10 13:24:07 +03:00
CTCaer
48334779a5 bdk: sdmmc: error reporting changes 
- Correct transfer error message
- Add debug print for deinit
 2024-06-08 17:41:11 +03:00
CTCaer
a34206df5b bdk: sdmmc: small changes 
- Log warning for comp pad calibration timeout
- Rename some func/defines
- Increase SDMMC1 power disable wait to 10ms
 No real perceived functionality change.
 2024-06-07 17:09:30 +03:00
CTCaer
9d79af231e bdk: use static where it should 2024-06-02 07:09:34 +03:00
CTCaer
f126486266 bdk: sdmmc: utilize block size defines 2024-03-12 15:47:14 +02:00
CTCaer
41d3565353 bdk: sdmmc: deduplicate function modes get 
And parse the whole info
 2023-12-27 15:01:20 +02:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up 
As per spec.
 2023-03-31 08:26:19 +03:00
CTCaer
b7164a629f bdk: sdmmc: allow max power limit to be set 
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
 2023-03-31 08:24:52 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support 
But disable it by default in the auto selection.
 2023-03-31 08:23:10 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer
22bdd0e0ff bdk: sdmmc: remove unused power limits 
Also name some magic numbers
 2023-02-11 23:15:28 +02:00
CTCaer
4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer
6257d20db9 bdk: emmc: add emmc_set_partition 
Additionally, add SDMMC index info to errors.
 2022-12-19 04:53:50 +02:00
CTCaer
197ce4c76f bdk: sdmmc: timing changes 
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
 2022-10-11 04:05:12 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
e5ddac5211 bdk: sdmmc: rename current limit to power limit 2022-06-25 05:53:04 +03:00
CTCaer
489e222aac bdk: sdmmc: expose csd/scr functions 2022-06-25 05:48:54 +03:00
CTCaer
c77c741c07 bdk: sdmmc: correct lower speed mode checks 
Both bus widths of 8 and 4 should be checked for HS200 support and host type support, instead of giving 8-bit bus width a free pass.
 2022-05-26 03:04:27 +03:00
CTCaer
ee465b98af bdk: sdmmc correct exit on eMMC < 4.0 modules 2022-02-15 00:24:53 +02:00
CTCaer
ef5790cc2c bdk: mc: always on ahb arbitration 
- Removed disables
- SDMMC code now just checks if it has access
 2022-01-29 01:29:02 +02:00
CTCaer
b08e36a7b0 bdk: add emmc ops 
- Add support for lower eMMC bus speed init in case of failures
- Add error count reporting
- Function names and defines changed from nx_emmc to emmc (except autorcm helper function)
- Enabling emuMMC support needs BDK_EMUMMC_ENABLE flag passed over
 2022-01-20 13:14:38 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
dcdf687a07 sdmmc: add support for sandisk emmc device report 2021-07-06 10:15:59 +03:00
CTCaer
a4a056128a sdmmc: Add support for SDSC cards 2021-02-06 04:18:30 +02:00
CTCaer
a8a45b215a nyx: Add emmc info about write cache and enhanced area 2021-02-06 03:44:27 +02:00