OmniNX/hekate
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ecbbc865bcb0131df1268a021c5f75af0b889d94
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65 Commits

Author SHA1 Message Date
CTCaer
55330b1bf5 bdk: pmc: refactor register defines and structs 2026-01-29 08:33:01 +02:00
CTCaer
3134af6e92 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-01-20 06:13:02 +02:00
CTCaer
8ab6f04243 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-01-12 03:57:39 +02:00
CTCaer
b5a6c8eb64 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2025-12-18 11:17:43 +02:00
CTCaer
8faa1a6690 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2025-12-18 09:54:26 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
20fa8382e6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2025-08-27 15:13:56 +03:00
CTCaer
3cde8b7d58 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2025-08-27 15:10:47 +03:00
CTCaer
05cc9b6985 bdk: refactor several comments and defines 2025-06-22 13:32:32 +03:00
CTCaer
e47b6ec19b bdk: hwinit: display changes 
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
 2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d bdk: hwinit: reorder no io power 
And make sure sdmmc iopower is not enabled after vdd disable.
 2024-07-02 17:56:20 +03:00
CTCaer
054c68f251 bdk: hwinit: power on all relevant rails 
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
 2024-06-08 12:21:15 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d bdk: fan: rename functions and add set from temp 
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
 2024-06-07 17:14:05 +03:00
CTCaer
14c482ddce bdk: display: remove max77620 gpio 7 enable 
It is actually not used at all.
So do not configure it to save power.
 2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33 bdk: hwinit: move LDO8 init in regulators init 
And also reorder it above I2C1 init (because of HOAG).
 2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab bdk: hwinit: move sd2 to hw init 
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
 2024-06-05 01:33:15 +03:00
CTCaer
05db43a97c bdk: hwinit: move down debug uart init 2024-06-02 07:44:22 +03:00
CTCaer
ae29f359ee bdk: hwinit: rename reinit_workaround to deinit 2024-05-19 10:49:25 +03:00
CTCaer
985c513770 bdk: hwinit: add arbiter config 2024-05-19 10:07:06 +03:00
CTCaer
7f98fb736a bdk: hwinit: reorder sdmmc1 reg disable 2023-12-25 04:07:26 +02:00
CTCaer
ce137852b7 bdk: change some defines and comments 2023-10-12 06:59:15 +03:00
CTCaer
b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer
27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer
17cdd5af0d bdk: hwdeinit: restore order of bpmp clock set 
Restore order of bpmp clock scale down in deinit, in order to decrease pressure on clock deinits.
 2023-02-22 14:48:43 +02:00
CTCaer
9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer
72abe60a3b bdk: hw init: remove support for broken hwinits 
It's 2023 already.
 2023-02-11 23:19:56 +02:00
CTCaer
114abba815 bdk: hw init: do not touch audio clocks on t210b01 2023-02-11 23:13:41 +02:00
CTCaer
5bb9a244ea bdk: utilize new gpio functions 2023-02-11 23:08:32 +02:00
CTCaer
0e1eece04f bdk: hw-init: remove charger forced enable 
Anything that doesn't manage it properly should fix itself.
(Like for example disabling charging on sleep or something. They should use the gpio equivalent.)
 2022-12-19 05:35:04 +02:00
CTCaer
4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer
d0b22bf374 bdk: manage host1x only in hw init 2022-12-19 05:14:39 +02:00
CTCaer
9d889e2c3e bdk: Add driver for VIC 
VIC is a HW engine that allows for frame/texture buffer manipulation.
 2022-10-11 06:41:38 +03:00
CTCaer
bfad719fcd bdk: small refactor 2022-10-11 06:16:38 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
9e613a7600 bdk: hwinit: simplify uart debug port paths 2022-05-13 03:56:59 +03:00
CTCaer
f7bf4af3ec bdk: uart: refactor and add new functionality 
- Allow to set CTS/RTS mode (only specific combos supported for now)
- Support the above modes in receiving
- Set 2 stop bits to decreases errors on high baudrates
 2022-05-08 05:45:16 +03:00
CTCaer
8327de8e2e bdk: replace NYX flag with proper flags 
- BDK_MINERVA_CFG_FROM_RAM: enables support for getting minerva configuration from nyx storage
- BDK_HW_EXTRA_DEINIT: enables extra deinit in hw_reinit_workaround
- BDK_SDMMC_OC_AND_EXTRA_PRINT: enables eMMC OC support (533 MB/s) and extra error printing
 2022-01-20 13:19:48 +02:00
CTCaer
853f10f774 bdk: pmc: update tzram defines 2022-01-20 12:13:35 +02:00
CTCaer
5e6a7c486b bdk: btn: enable HOME button as input 2022-01-16 01:05:42 +02:00
CTCaer
1a9c6bf983 bdk: correct reg init as per TRM 2022-01-16 01:04:52 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
c801ef8dda bdk: use size defines where applicable 2021-10-01 15:03:18 +03:00
CTCaer
a1910156d8 bdk: hwinit: save boot reason for later usage 2021-10-01 14:32:42 +03:00
CTCaer
7c72c9777a fuse/hwinit: move automatic SBK set into fuse 2021-08-28 16:46:15 +03:00
CTCaer
c29db97f73 hwinit/joycon: move uart clock deinits to joycon driver 2021-05-11 10:24:48 +03:00
CTCaer
28008ac7ac hwinit: add seamless display (L4T Linux/Android) 
Initial support is for coreboot based preloading.
 2021-04-11 09:18:55 +03:00
CTCaer
a7bf8bf118 se: Refactor with proper names 
Additionally fix some bugs in rsa access control
 2021-02-06 02:55:58 +02:00
CTCaer
8fc5267110 tmp451: Show correct temperature for T210B01 
The thermal measurement substrate transistor was changed in Mariko SoCs.
This ensures that it's properly offset by -12.5 °C.
 2021-01-14 17:58:23 +02:00