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ca8717d4a74aa4fa9a65e5fcf8ebc9c5316cfcdf
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182 Commits

Author SHA1 Message Date
CTCaer
d14a1fb7d6 bdk: move exception type base away from IRQ stack 
Allow a more heavy stack usage by IRQ handlers.
 2026-02-12 21:32:43 +02:00
CTCaer
b297e58bc8 bdk: add missing header guards 2026-01-29 09:07:22 +02:00
CTCaer
55330b1bf5 bdk: pmc: refactor register defines and structs 2026-01-29 08:33:01 +02:00
CTCaer
0da69efd07 bdk: pinmux: always detach I2C4 pins from I2C3 pm 
Generally I2C3 communication can work via I2C3 or I2C4 pins.
Defaults are fine as long as one of the pin groups are floating or grounded or
both share I2C traces.

In NX boards I2C4 SDA is used for GC and connected to 1V8.
So if a GC is slotted, I2C3 works, if not, no communication is possible.

This config was done previously inside I2C3 consumer driver (touchscreen).
Now it's moved inside pinmux_config_i2c.
 2026-01-21 23:49:59 +02:00
CTCaer
3134af6e92 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-01-20 06:13:02 +02:00
CTCaer
8ab6f04243 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-01-12 03:57:39 +02:00
CTCaer
0cab56293d bdk: ccplex: do not disable mselect on cpu pwrgate 2025-12-25 12:51:37 +02:00
CTCaer
b5a6c8eb64 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2025-12-18 11:17:43 +02:00
CTCaer
8faa1a6690 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2025-12-18 09:54:26 +02:00
CTCaer
20a50988c5 bdk: fuse: return array size with fuse_read_array 2025-12-17 06:41:52 +02:00
CTCaer
8d6bb5f427 bdk: clock: update some defines 2025-12-17 04:33:40 +02:00
CTCaer
a6d4e5adaa bdk: clock: add i2c to the errata affected list 2025-11-27 12:12:13 +02:00
CTCaer
4a24956f3a bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2025-11-27 12:04:12 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
e7783f0bd7 bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2025-11-26 16:53:19 +02:00
CTCaer
e50ad58d61 bdk: clock: add sdmmc1 to the errata affected list 2025-11-26 16:47:29 +02:00
CTCaer
0a63fa19a3 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2025-11-26 16:46:11 +02:00
CTCaer
19285745b5 bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2025-11-26 14:48:47 +02:00
CTCaer
9c028cd94a bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2025-11-26 14:37:14 +02:00
CTCaer
a2ea3fb08e bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2025-11-26 14:33:56 +02:00
CTCaer
813346f796 bdk: bpmp: add binX clock defines 2025-11-11 13:52:00 +02:00
CTCaer
260e28e628 bdk: fuse: add sense function 2025-11-11 13:28:44 +02:00
CTCaer
602945d918 bdk: fuse: add extra info on regs 2025-11-11 13:27:36 +02:00
CTCaer
7e01438ed3 bdk: fuse: correct masking on array read cmd 2025-11-11 13:27:13 +02:00
CTCaer
2c66b17f42 bdk: t210: add mc channel macros 2025-11-11 13:24:06 +02:00
CTCaer
20fa8382e6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2025-08-27 15:13:56 +03:00
CTCaer
3cde8b7d58 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2025-08-27 15:10:47 +03:00
CTCaer
f354f0e5bd bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2025-08-27 14:48:35 +03:00
CTCaer
ea3a60f516 bdk: clock: simplify logic 
Simplify logic for clock enable and sdmmc clock management
 2025-08-27 14:44:41 +03:00
CTCaer
b4b3133570 bdk: clock: remove non existent module ids 
And add comments to special handling ones
 2025-08-27 14:41:27 +03:00
CTCaer
c63ccd0cdc bdk: pmc: rename pmc_enable_partition 2025-08-27 14:39:44 +03:00
CTCaer
8be2c5506e bdk: clock: wait for PLLD to lock when set 2025-08-08 15:58:32 +03:00
CTCaer
05cc9b6985 bdk: refactor several comments and defines 2025-06-22 13:32:32 +03:00
CTCaer
d851c16ce7 bdk: clock: refactor common PLL defines 2025-06-22 12:47:26 +03:00
CTCaer
c07a155cc1 bdk: small refactoring 2025-04-30 08:14:32 +03:00
CTCaer
14413ae6bd bdk: timer: restore rtc timer spinlock 2024-10-10 18:22:03 +03:00
CTCaer
edf00d8e51 bdk: bpmp: add state set function 
Some states are controlled via software. So add a function for that.
 2024-10-04 21:54:58 +03:00
CTCaer
1a98e3a702 bdk: irq: disable irq if handler error 2024-10-04 21:53:17 +03:00
CTCaer
8bf3bee08b bdk: uart: fix fifo clear 
- Do not clear fifo for everything if not needed
- Correct fifo clear checks
 2024-10-04 21:52:24 +03:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
e47b6ec19b bdk: hwinit: display changes 
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
 2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d bdk: hwinit: reorder no io power 
And make sure sdmmc iopower is not enabled after vdd disable.
 2024-07-02 17:56:20 +03:00
CTCaer
054c68f251 bdk: hwinit: power on all relevant rails 
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
 2024-06-08 12:21:15 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d bdk: fan: rename functions and add set from temp 
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
 2024-06-07 17:14:05 +03:00
CTCaer
14c482ddce bdk: display: remove max77620 gpio 7 enable 
It is actually not used at all.
So do not configure it to save power.
 2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33 bdk: hwinit: move LDO8 init in regulators init 
And also reorder it above I2C1 init (because of HOAG).
 2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab bdk: hwinit: move sd2 to hw init 
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
 2024-06-05 01:33:15 +03:00
CTCaer
bd55a3e756 bdk: clock: always set DISPA source 
No need to distinguish between LP or HS.
Setting the same value doesn't glitch.
 2024-06-02 08:00:42 +03:00
CTCaer
b01cc2432f bdk: irq: remove ack source 
HW interrupts can't be managed by FIR.
Only actual hw can clear the interrupt.
 2024-06-02 07:46:18 +03:00