Commit Graph

5 Commits

Author SHA1 Message Date
CTCaer
b6ec6a8f6e minerva: update tov1.6_T210/v0.1_T21X
T21X v0.1:
- Add IRB/no table support
T210 v1.6/Common:
- Add a proper table for 8GB T210 config instead of editing a 4GB one
- Increase timeout to 2ms
- Generally improve checks and guard against unknown SoCs/SKUs
- Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs
2025-12-17 05:58:09 +02:00
CTCaer
dad9abe93d minerva: update to v1.5
- "Perf" hack removal (match L4T mini Minerva)
 It's not a performance hack, it just kills low power modes.
 If wanted in L4T, use HP Mode in `ram_oc_opt`.
- Simplify of burst regs config
- Refactor of several bit defines and variables
2025-08-27 15:45:58 +03:00
CTCaer
05833bb38c minerva: update to v1.4
- Correct Zqlatch period checks
- Update periodic training
- Simplify some logic
- Fix some mr13 values
- Separate EMC channel enums from macros
- Add extra reg flushes
- Fix tree margin comparison signedness
 By using incorrect signedness on tree margins the delta taps would always apply.
 By casting margins to integer it now properly checks if it should apply delta taps on the new trimmers.
 This fixes a bug that exists in every Nvidia emc dvfs code.
2021-05-11 10:23:08 +03:00
CTCaer
66c4f30bdf minerva: Update to v1.2 and use only integers
Additionally remove support for DRAM types that Switch platform does not have.

This will reduce periodic training cost to 30us from 6ms.
2019-12-04 21:46:33 +02:00
Kostas Missos
cfef8b4f72 Update libminerva to v1.1 2018-11-10 13:30:17 +02:00