CTCaer
8d6bb5f427
bdk: clock: update some defines
2025-12-17 04:33:40 +02:00
CTCaer
9c028cd94a
bdk: clock: streamline sdmmc func naming
...
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
2025-11-26 14:37:14 +02:00
CTCaer
a2ea3fb08e
bdk: clock: use SET/CLR registers for all modules
...
This is not mandatory but removes unnecessary load-mask/or-stores.
On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
2025-11-26 14:33:56 +02:00
CTCaer
ea3a60f516
bdk: clock: simplify logic
...
Simplify logic for clock enable and sdmmc clock management
2025-08-27 14:44:41 +03:00
CTCaer
b4b3133570
bdk: clock: remove non existent module ids
...
And add comments to special handling ones
2025-08-27 14:41:27 +03:00
CTCaer
d851c16ce7
bdk: clock: refactor common PLL defines
2025-06-22 12:47:26 +03:00
CTCaer
9e239df39e
bdk: constify various args
2024-10-04 21:45:57 +03:00
CTCaer
e47b6ec19b
bdk: hwinit: display changes
...
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
2024-07-02 17:59:14 +03:00
CTCaer
9ba7c44b89
bdk: clock: use real source clock dividers
...
Use CLK_SRC_DIV macro in order to have the actual divider showing.
2024-03-13 02:01:01 +02:00
CTCaer
191a0533d9
bdk: clock: add more known pto ids
2023-06-09 10:29:47 +03:00
CTCaer
76a5facbc3
bdk: clock: rename clock_t to clk_rst_t
...
To avoid redefines when standard math header is used.
2023-03-31 08:18:45 +03:00
CTCaer
9d889e2c3e
bdk: Add driver for VIC
...
VIC is a HW engine that allows for frame/texture buffer manipulation.
2022-10-11 06:41:38 +03:00
CTCaer
70523e404f
bdk: whitespace refactor
2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108
bdk: migrate timers/sleeps to timer driver
2022-06-27 10:22:19 +03:00
CTCaer
f452d916c9
bdk: clock: add ext peripheral clock control
2022-05-09 06:08:39 +03:00
CTCaer
b9f40fed7a
bdk: di: move plld setup code out of display obj
2022-05-08 04:41:05 +03:00
CTCaer
3f65a30b2e
bdk: more atf prep
2022-02-15 00:14:53 +02:00
CTCaer
10b479dc1c
bdk: clock: add apb/ahb clock control
2022-01-20 12:32:57 +02:00
CTCaer
3dd12321f8
bdk: add activity monitor driver
2022-01-20 12:32:02 +02:00
CTCaer
70504c295e
bdk: various functionality independent changes
2022-01-16 01:03:24 +02:00
CTCaer
bcec028b0f
clock: update device frequency getter function
...
- Add missing write commits
- Remove hardcoded values
2021-09-17 23:16:43 +03:00
CTCaer
8f9d52aa89
clock: move pllx enable to clock object
2021-09-17 23:13:53 +03:00
CTCaer
11ca6caf5f
clock: Add more defines and simplify some logic
2020-12-26 17:28:08 +02:00
CTCaer
15afdf53e4
clock: Add module actual frequency getter
2020-12-26 17:25:23 +02:00
CTCaer
a1188505e8
usb: Add XUSB support mainly for T210B01
2020-12-02 01:13:52 +02:00
CTCaer
cabaa6cfb8
Utilize BIT macro everywhere
2020-11-26 01:41:45 +02:00
CTCaer
0b314d7f21
clock: Move UTMIPLL init from USB to clock
2020-11-15 14:43:36 +02:00
CTCaer
8305058cf5
clock: Move PLLU init/deinit from USB to clock
2020-11-15 14:42:01 +02:00
CTCaer
e158d9bc00
clk: Refactor CLK devices bits
2020-07-17 16:50:17 +03:00
CTCaer
6e256d29c7
Utilize hekate's BDK for hekate main and Nyx
2020-06-14 16:45:45 +03:00
CTCaer
185526d134
Introducing Bootloader Development Kit (BDK)
...
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.
Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.
Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.
This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00
