CTCaer
813346f796
bdk: bpmp: add binX clock defines
2025-11-11 13:52:00 +02:00
CTCaer
260e28e628
bdk: fuse: add sense function
2025-11-11 13:28:44 +02:00
CTCaer
602945d918
bdk: fuse: add extra info on regs
2025-11-11 13:27:36 +02:00
CTCaer
7e01438ed3
bdk: fuse: correct masking on array read cmd
2025-11-11 13:27:13 +02:00
CTCaer
2c66b17f42
bdk: t210: add mc channel macros
2025-11-11 13:24:06 +02:00
CTCaer
20fa8382e6
bdk: hwinit: refactor MBIST WAR & add description
...
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
2025-08-27 15:13:56 +03:00
CTCaer
3cde8b7d58
bdk: hwinit: fix RAM_SVOP_PDP try no 2
...
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
2025-08-27 15:10:47 +03:00
CTCaer
f354f0e5bd
bdk: add some t210 and fuses defines
...
PGUP tag register can be used to identify which cpu we are running on.
2025-08-27 14:48:35 +03:00
CTCaer
ea3a60f516
bdk: clock: simplify logic
...
Simplify logic for clock enable and sdmmc clock management
2025-08-27 14:44:41 +03:00
CTCaer
b4b3133570
bdk: clock: remove non existent module ids
...
And add comments to special handling ones
2025-08-27 14:41:27 +03:00
CTCaer
c63ccd0cdc
bdk: pmc: rename pmc_enable_partition
2025-08-27 14:39:44 +03:00
CTCaer
8be2c5506e
bdk: clock: wait for PLLD to lock when set
2025-08-08 15:58:32 +03:00
CTCaer
05cc9b6985
bdk: refactor several comments and defines
2025-06-22 13:32:32 +03:00
CTCaer
d851c16ce7
bdk: clock: refactor common PLL defines
2025-06-22 12:47:26 +03:00
CTCaer
c07a155cc1
bdk: small refactoring
2025-04-30 08:14:32 +03:00
CTCaer
14413ae6bd
bdk: timer: restore rtc timer spinlock
2024-10-10 18:22:03 +03:00
CTCaer
edf00d8e51
bdk: bpmp: add state set function
...
Some states are controlled via software. So add a function for that.
2024-10-04 21:54:58 +03:00
CTCaer
1a98e3a702
bdk: irq: disable irq if handler error
2024-10-04 21:53:17 +03:00
CTCaer
8bf3bee08b
bdk: uart: fix fifo clear
...
- Do not clear fifo for everything if not needed
- Correct fifo clear checks
2024-10-04 21:52:24 +03:00
CTCaer
9e239df39e
bdk: constify various args
2024-10-04 21:45:57 +03:00
CTCaer
e47b6ec19b
bdk: hwinit: display changes
...
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d
bdk: hwinit: reorder no io power
...
And make sure sdmmc iopower is not enabled after vdd disable.
2024-07-02 17:56:20 +03:00
CTCaer
054c68f251
bdk: hwinit: power on all relevant rails
...
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
2024-06-08 12:21:15 +03:00
CTCaer
85eb5489fe
bdk: pmc: rename io/det power defines
2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d
bdk: fan: rename functions and add set from temp
...
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
2024-06-07 17:14:05 +03:00
CTCaer
14c482ddce
bdk: display: remove max77620 gpio 7 enable
...
It is actually not used at all.
So do not configure it to save power.
2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33
bdk: hwinit: move LDO8 init in regulators init
...
And also reorder it above I2C1 init (because of HOAG).
2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab
bdk: hwinit: move sd2 to hw init
...
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
2024-06-05 01:33:15 +03:00
CTCaer
bd55a3e756
bdk: clock: always set DISPA source
...
No need to distinguish between LP or HS.
Setting the same value doesn't glitch.
2024-06-02 08:00:42 +03:00
CTCaer
b01cc2432f
bdk: irq: remove ack source
...
HW interrupts can't be managed by FIR.
Only actual hw can clear the interrupt.
2024-06-02 07:46:18 +03:00
CTCaer
05db43a97c
bdk: hwinit: move down debug uart init
2024-06-02 07:44:22 +03:00
CTCaer
9d79af231e
bdk: use static where it should
2024-06-02 07:09:34 +03:00
CTCaer
7a74761da9
bdk: bpmp: add and use bpmp_clk_rate_relaxed
2024-06-02 06:51:06 +03:00
CTCaer
927489d2da
bdk: add missed defines
2024-05-19 10:50:25 +03:00
CTCaer
ae29f359ee
bdk: hwinit: rename reinit_workaround to deinit
2024-05-19 10:49:25 +03:00
CTCaer
985c513770
bdk: hwinit: add arbiter config
2024-05-19 10:07:06 +03:00
CTCaer
ec2e62236a
bdk: pinmux: add i2s pin config
2024-04-25 04:52:13 +03:00
CTCaer
9ba7c44b89
bdk: clock: use real source clock dividers
...
Use CLK_SRC_DIV macro in order to have the actual divider showing.
2024-03-13 02:01:01 +02:00
CTCaer
9a520d63a6
bdk: smmu: refactor driver and allow other asid
2024-03-13 01:54:46 +02:00
CTCaer
20e661fc01
bdk: refactor flow control defines
2024-03-13 01:50:45 +02:00
CTCaer
fb31cb2926
bdk: ccplex: add no rst vector lock & powergating
...
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
2024-03-13 01:37:52 +02:00
CTCaer
b584a3f53a
bdk: add several defines
2023-12-25 04:08:34 +02:00
CTCaer
7f98fb736a
bdk: hwinit: reorder sdmmc1 reg disable
2023-12-25 04:07:26 +02:00
CTCaer
87c50732c0
bdk: fuse: simplify idle wait
2023-12-25 03:47:26 +02:00
CTCaer
504659a39b
bdk: actmon: switch to averaged sampling
2023-12-25 03:46:05 +02:00
CTCaer
ce137852b7
bdk: change some defines and comments
2023-10-12 06:59:15 +03:00
CTCaer
f2bdc3f47c
bdk: i2c: fix stack buffer overflow
2023-08-07 21:02:20 +03:00
CTCaer
1e28320e5a
bdk: t210: add more mmio addresses
...
And simplify relevant drivers that hardcoded them.
2023-07-31 16:59:15 +03:00
CTCaer
9187fa7a8c
bdk: fuse: add all t210b01 fuses
...
And use B01 to distinguish the ones only on that SoC.
2023-07-22 07:10:12 +03:00
CTCaer
b674624ad0
bdk: timer: add instruction sleep
...
usage:
`isleep(ILOOP(instructions))`
Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
2023-06-09 10:33:11 +03:00
