5 Commits

Author	SHA1	Message	Date
CTCaer	b6ec6a8f6e	minerva: update tov1.6_T210/v0.1_T21X ... T21X v0.1: - Add IRB/no table support T210 v1.6/Common: - Add a proper table for 8GB T210 config instead of editing a 4GB one - Increase timeout to 2ms - Generally improve checks and guard against unknown SoCs/SKUs - Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs	2025-12-17 05:58:09 +02:00
CTCaer	d8d15bde44	lib: minerva: add Samsung 8GB support ... And remove frequencies smaller than deep sleep frequency from the tables.	2023-06-08 04:50:59 +03:00
CTCaer	d37fe213d7	mtc: Name sdram ids	2020-06-14 17:39:39 +03:00
Kostas Missos	cfef8b4f72	Update libminerva to v1.1	2018-11-10 13:30:17 +02:00
Kostas Missos	cae9044c17	Minerva our DRAM trainer ... Supports up to 1600MHz and periodic training. For more check here: https://github.com/CTCaer/minerva_tc	2018-11-04 03:15:32 +02:00