From fee75711351cff1f8d3f65f5b87766f217946435 Mon Sep 17 00:00:00 2001 From: CTCaer Date: Wed, 27 Aug 2025 15:02:27 +0300 Subject: [PATCH] bdk: mc: carveouts are not set by cfg so fix them For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them. So add which need different value from reset and also make sure that data is flushed for WPR config. --- bdk/mem/mc.c | 72 ++++++++++++++++++++++++++++++++++++---------------- bdk/mem/mc.h | 3 +-- 2 files changed, 51 insertions(+), 24 deletions(-) diff --git a/bdk/mem/mc.c b/bdk/mem/mc.c index ac810940..52552142 100644 --- a/bdk/mem/mc.c +++ b/bdk/mem/mc.c @@ -17,60 +17,88 @@ #include #include +#include #include #include #include #define HOS_WPR1_BASE 0x80020000 -void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock) +void mc_config_carveout_hos() { - MC(MC_SEC_CARVEOUT_BOM) = bom; - MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb; - if (lock) - MC(MC_SEC_CARVEOUT_REG_CTRL) = 1; -} - -void mc_config_carveout() -{ - // Enable ACR GSR3. + // Enable ACR GSR3 and flush data to ram. *(u32 *)(HOS_WPR1_BASE + SZ_256K - sizeof(u32)) = ACR_GSC3_ENABLE_MAGIC; + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); // Set VPR CYA TRUSTED DEFAULT. MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = VPR_OVR0_CYA_TRUST_DEFAULT; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0; - MC(MC_VIDEO_PROTECT_BOM) = 0; + + // Disable VPR carveout. + MC(MC_VIDEO_PROTECT_BOM) = 0; + MC(MC_VIDEO_PROTECT_SIZE_MB) = 0; MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED; - // Configure TZDRAM carveout @ 0x90000000, 1MB. - //mc_config_tzdram_carveout(0x90000000, 1, false); - mc_config_tzdram_carveout(0, 0, true); + // Disable TZDRAM carveout. + MC(MC_SEC_CARVEOUT_BOM) = 0; + MC(MC_SEC_CARVEOUT_SIZE_MB) = 0; + MC(MC_SEC_CARVEOUT_REG_CTRL) = BIT(0); - MC(MC_MTS_CARVEOUT_BOM) = 0; - MC(MC_MTS_CARVEOUT_REG_CTRL) = 1; + // Disable CPU FW carveout. + MC(MC_MTS_CARVEOUT_BOM) = 0; + MC(MC_MTS_CARVEOUT_SIZE_MB) = 0; + MC(MC_MTS_CARVEOUT_REG_CTRL) = BIT(0); + // Disable GEN1 carveout. MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED | SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | SEC_CARVEOUT_CFG_APERTURE_ID(0) | SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; - MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000; + // Enable GEN2 carveout as WPR1. + MC(MC_SECURITY_CARVEOUT2_BOM) = HOS_WPR1_BASE; + MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = SZ_256K / SZ_128K; MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2; + MC(MC_SECURITY_CARVEOUT2_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_RD_FALCON_LS | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_LS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(2) | + SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; + // Prepare GEN3 carveout as WPR2. + MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2; + MC(MC_SECURITY_CARVEOUT3_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_RD_FALCON_LS | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_LS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(3) | + SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; + + // Disable GEN4 carveout. MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0; MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE | SEC_CARVEOUT_CFG_LOCKED | SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | SEC_CARVEOUT_CFG_RD_NS | SEC_CARVEOUT_CFG_WR_NS; + // Disable GEN5 carveout. MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0; MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE | SEC_CARVEOUT_CFG_LOCKED | SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | diff --git a/bdk/mem/mc.h b/bdk/mem/mc.h index 300bbfdc..05a8ad9e 100644 --- a/bdk/mem/mc.h +++ b/bdk/mem/mc.h @@ -21,8 +21,7 @@ #include void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock); -void mc_config_carveout(); -void mc_config_carveout_finalize(); +void mc_config_carveout_hos(); void mc_enable_ahb_redirect(); void mc_disable_ahb_redirect(); bool mc_client_has_access(void *address);