From f354f0e5bd92b65fccaed7a7121800d100aac8af Mon Sep 17 00:00:00 2001 From: CTCaer Date: Wed, 27 Aug 2025 14:48:35 +0300 Subject: [PATCH] bdk: add some t210 and fuses defines PGUP tag register can be used to identify which cpu we are running on. --- bdk/soc/fuse.h | 7 +++++-- bdk/soc/t210.h | 10 ++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/bdk/soc/fuse.h b/bdk/soc/fuse.h index a417503d..a5025e17 100644 --- a/bdk/soc/fuse.h +++ b/bdk/soc/fuse.h @@ -201,7 +201,7 @@ #define FUSE_RESERVED_ODM29_B01 0x294 #define FUSE_APB2JTAG_DISABLE 0x298 -#define FUSE_ODM_INFO 0x29C +#define FUSE_ODM_INFO 0x29C // Debug features disable. #define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8 #define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0 @@ -212,6 +212,9 @@ #define FUSE_WOA_SKU_FLAG 0x2C0 #define FUSE_ECO_RESERVE_1 0x2C4 #define FUSE_GCPLEX_CONFIG_FUSE 0x2C8 +#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0) +#define FUSE_GPU_VPR_ENABLED BIT(1) +#define FUSE_GPU_WPR_ENABLED BIT(2) #define FUSE_PRODUCTION_MONTH 0x2CC #define FUSE_RAM_REPAIR_INDICATOR 0x2D0 #define FUSE_TSENSOR9_CALIB 0x2D4 @@ -223,7 +226,7 @@ #define FUSE_OPT_GPU_DISABLE_CP1 0x2F0 #define FUSE_SPARE_ENDIS 0x2F4 #define FUSE_ECO_RESERVE_0 0x2F8 -#define FUSE_RESERVED_CALIB0 0x304 +#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration. #define FUSE_RESERVED_CALIB1 0x308 #define FUSE_OPT_GPU_TPC0_DISABLE 0x30C #define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310 diff --git a/bdk/soc/t210.h b/bdk/soc/t210.h index eaf59dfb..a95e10cd 100644 --- a/bdk/soc/t210.h +++ b/bdk/soc/t210.h @@ -38,6 +38,7 @@ #define SOR1_BASE 0x54580000 #define GPU_BASE 0x57000000 #define GPU_USER_BASE 0x58000000 +#define PG_BASE 0x60000000 #define RES_SEMAPH_BASE 0x60001000 #define ARB_SEMAPH_BASE 0x60002000 #define ARB_PRI_BASE 0x60003000 @@ -114,6 +115,7 @@ #define SOR1(off) MMIO_REG32(SOR1_BASE, off) #define GPU(off) MMIO_REG32(GPU_BASE, off) #define GPU_USER(off) MMIO_REG32(GPU_USER_BASE, off) +#define PG(off) MMIO_REG32(PG_BASE, off) #define ARB_PRI(off) MMIO_REG32(ARB_PRI_BASE, off) #define ICTLR(cidx, off) MMIO_REG32(ICTLR_BASE + (0x100 * (cidx)), off) #define TMR(off) MMIO_REG32(TMR_BASE, off) @@ -376,4 +378,12 @@ #define NVDEC_SA_KEYSLOT_OTF 0x210C #define NVDEC_SA_KEYSLOT_GLOBAL_RW 0x2118 #define NVDEC_VPR_ALL_OTF_GOTO_VPR 0x211C + +/* PG registers */ +#define PG_UP_TAG 0x0 // Changes depending on what does the reg read request. +#define TAG_PID_CCPLEX 0x55555555 +#define TAG_PID_BPMP 0xAAAAAAAA +#define TAG_PID_COP2 0x99999999 +#define TAG_PID_OTHER 0xCCCCCCCC + #endif