minerva: update to v1.5

- "Perf" hack removal (match L4T mini Minerva)
 It's not a performance hack, it just kills low power modes.
 If wanted in L4T, use HP Mode in `ram_oc_opt`.
- Simplify of burst regs config
- Refactor of several bit defines and variables

modules/hekate_libsys_minerva/mtc.h

@@ -2,7 +2,7 @@
  * Minerva Training Cell
  * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
  *
- * Copyright (c) 2018-2022 CTCaer  <ctcaer@gmail.com>
+ * Copyright (c) 2018-2025 CTCaer  <ctcaer@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -63,7 +63,7 @@
 #define NEEDS_TRAINING_SWAP_RANK       BIT(8)
 #define NEEDS_TRAINING_IN_SELF_REFRESH BIT(9)
 
-#define NEEDS_TRISTATE_TRAINING   (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF | \
+#define NEEDS_TRAINING            (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF | \
 								   NEEDS_TRAINING_QUSE | NEEDS_TRAINING_WR |    \
 								   NEEDS_TRAINING_WR_VREF | NEEDS_TRAINING_RD | \
 								   NEEDS_TRAINING_RD_VREF)

modules/hekate_libsys_minerva/mtc_mc_emc_regs.h

@@ -2,7 +2,7 @@
  * Minerva Training Cell
  * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
  *
- * Copyright (c) 2018 CTCaer  <ctcaer@gmail.com>
+ * Copyright (c) 2018-2025 CTCaer  <ctcaer@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,13 @@
 #define  CLKCHANGE_COMPLETE_INT (1 << 4)
 
 #define EMC_DBG                       0x8
+#define  EMC_DBG_READ_MUX_ACTIVE        BIT(0)
+#define  EMC_DBG_WRITE_MUX_ACTIVE       BIT(1)
+#define  EMC_DBG_CFG_SWAP_ACTIVE_ONLY   (0 << 26u)
+#define  EMC_DBG_CFG_SWAP_SWAP          (1 << 26u)
+#define  EMC_DBG_CFG_SWAP_ASSEMBLY_ONLY (2 << 26u)
+#define  EMC_DBG_CFG_SWAP_MASK          (3 << 26u)
+#define  EMC_DBG_WRITE_ACTIVE_ONLY      BIT(30)
 #define EMC_CFG                       0xC
 #define EMC_PIN                       0x24
 #define EMC_TIMING_CONTROL            0x28
@@ -628,4 +635,4 @@
 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0
 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16
 
-#endif
+#endif