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bdk: clock: refactor common PLL defines

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CTCaer
2025-06-22 12:47:26 +03:00
parent 5e8b01f727
commit d851c16ce7
3 changed files with 23 additions and 27 deletions
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2
bdk/mem/sdram.c
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@@ -260,7 +260,7 @@ static void _sdram_config_t210(const sdram_params_t210_t *params)
u32 pllm_div = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20);
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div;
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div | PLLCX_BASE_ENABLE;
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div | PLL_BASE_ENABLE;
u32 wait_end = get_tmr_us() + 300;
while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & BIT(27)))