diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c
index de2dbbbe..405fae51 100644
--- a/bdk/sec/tsec.c
+++ b/bdk/sec/tsec.c
@@ -91,10 +91,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 	if (type == TSEC_FW_TYPE_NEW)
 	{
 		// Disable all CCPLEX core rails.
-		pmc_enable_partition(POWER_RAIL_CE0, DISABLE);
-		pmc_enable_partition(POWER_RAIL_CE1, DISABLE);
-		pmc_enable_partition(POWER_RAIL_CE2, DISABLE);
-		pmc_enable_partition(POWER_RAIL_CE3, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE0, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE1, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE2, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE3, DISABLE);
 
 		// Enable AHB aperture and set it to full mmio.
 		mc_enable_ahb_redirect();
diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c
index c01a8925..a5350a50 100644
--- a/bdk/soc/ccplex.c
+++ b/bdk/soc/ccplex.c
@@ -90,11 +90,11 @@ void ccplex_boot_cpu0(u32 entry, bool lock)
 	CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
 
 	// Enable CPU main rail.
-	pmc_enable_partition(POWER_RAIL_CRAIL, ENABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_CRAIL, ENABLE);
 	// Enable cluster 0 non-CPU rail.
-	pmc_enable_partition(POWER_RAIL_C0NC,  ENABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_C0NC,  ENABLE);
 	// Enable CPU0 rail.
-	pmc_enable_partition(POWER_RAIL_CE0,   ENABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_CE0,   ENABLE);
 
 	// Request and wait for RAM repair. Needed for the Fast cluster.
 	FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = RAM_REPAIR_REQ;
@@ -150,11 +150,11 @@ void ccplex_powergate_cpu0()
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_SET) = BIT(CLK_V_MSELECT);
 
 	// Disable CE0.
-	pmc_enable_partition(POWER_RAIL_CE0,   DISABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_CE0,   DISABLE);
 	// Disable cluster 0 non-CPU.
-	pmc_enable_partition(POWER_RAIL_C0NC,  DISABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_C0NC,  DISABLE);
 	// Disable CPU rail.
-	pmc_enable_partition(POWER_RAIL_CRAIL, DISABLE);
+	pmc_domain_pwrgate_set(POWER_RAIL_CRAIL, DISABLE);
 
 	clock_disable_coresight();
 
diff --git a/bdk/soc/pmc.c b/bdk/soc/pmc.c
index 472b22cd..2f5d4cc8 100644
--- a/bdk/soc/pmc.c
+++ b/bdk/soc/pmc.c
@@ -99,17 +99,26 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
 	}
 }
 
-int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
+/*
+ * !TODO: Non CCPLEX power domains power gating/ungating.
+ * Power gating: clock should be in reset if enabled and then
+ * pmc_domain_pwrgate_set is run.
+ * Power ungating: run pmc_domain_pwrgate_set, enable clocks and keep in
+ * reset, remove clamping, remove reset, run mbist war if T210 and then clocks
+ * can be disabled.
+ */
+
+int pmc_domain_pwrgate_set(pmc_power_rail_t part, u32 enable)
 {
 	u32 part_mask = BIT(part);
 	u32 desired_state = enable << part;
 
-	// Check if the partition has the state we want.
+	// Check if the power domain has the state we want.
 	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
 		return 1;
 
 	u32 i = 5001;
-	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
+	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & PMC_PWRGATE_TOGGLE_START)
 	{
 		usleep(1);
 		i--;
@@ -118,7 +127,7 @@ int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
 	}
 
 	// Toggle power gating.
-	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
+	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | PMC_PWRGATE_TOGGLE_START;
 
 	i = 5001;
 	while (i > 0)
diff --git a/bdk/soc/pmc.h b/bdk/soc/pmc.h
index ea8aaa9d..def67d9b 100644
--- a/bdk/soc/pmc.h
+++ b/bdk/soc/pmc.h
@@ -37,6 +37,7 @@
 #define  PMC_CNTRL_SHUTDOWN_OE             BIT(22)
 #define APBDEV_PMC_SEC_DISABLE       0x4
 #define APBDEV_PMC_PWRGATE_TOGGLE    0x30
+#define  PMC_PWRGATE_TOGGLE_START          BIT(8)
 #define APBDEV_PMC_PWRGATE_STATUS    0x38
 #define APBDEV_PMC_NO_IOPOWER        0x44
 #define  PMC_NO_IOPOWER_MEM                BIT(7)
@@ -219,19 +220,14 @@ typedef enum _pmc_sec_lock_t
 typedef enum _pmc_power_rail_t
 {
 	POWER_RAIL_CRAIL = 0,
-	POWER_RAIL_3D0   = 1,
-	POWER_RAIL_VENC  = 2,
+	POWER_RAIL_VE    = 2,
 	POWER_RAIL_PCIE  = 3,
-	POWER_RAIL_VDEC  = 4,
-	POWER_RAIL_L2C   = 5,
-	POWER_RAIL_MPE   = 6,
-	POWER_RAIL_HEG   = 7,
+	POWER_RAIL_NVENC = 6,
 	POWER_RAIL_SATA  = 8,
 	POWER_RAIL_CE1   = 9,
 	POWER_RAIL_CE2   = 10,
 	POWER_RAIL_CE3   = 11,
 	POWER_RAIL_CELP  = 12,
-	POWER_RAIL_3D1   = 13,
 	POWER_RAIL_CE0   = 14,
 	POWER_RAIL_C0NC  = 15,
 	POWER_RAIL_C1NC  = 16,
@@ -251,6 +247,6 @@ typedef enum _pmc_power_rail_t
 } pmc_power_rail_t;
 
 void pmc_scratch_lock(pmc_sec_lock_t lock_mask);
-int  pmc_enable_partition(pmc_power_rail_t part, u32 enable);
+int  pmc_domain_pwrgate_set(pmc_power_rail_t part, u32 enable);
 
 #endif