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minerva: update tov1.6_T210/v0.1_T21X

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T21X v0.1:
- Add IRB/no table support
T210 v1.6/Common:
- Add a proper table for 8GB T210 config instead of editing a 4GB one
- Increase timeout to 2ms
- Generally improve checks and guard against unknown SoCs/SKUs
- Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs
This commit is contained in:
CTCaer
2025-12-17 05:58:09 +02:00
parent 0db758592a
commit b6ec6a8f6e
5 changed files with 2437 additions and 123 deletions
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14
modules/hekate_libsys_minerva/mtc_mc_emc_regs.h
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@@ -1,6 +1,6 @@
/*
* Minerva Training Cell
* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
* DRAM Training for Tegra X1 SoC. Supports LPDDR4.
*
* Copyright (c) 2018-2025 CTCaer <ctcaer@gmail.com>
*
@@ -20,6 +20,16 @@
#ifndef _MTC_MC_EMC_REGS_H_
#define _MTC_MC_EMC_REGS_H_
/* APB misc registers */
#define APB_MISC_GP_HIDREV 0x804
#define HIDREV_MAJOR_T210 0x1
#define HIDREV_MAJOR_T210B01 0x2
#define HIDREV_CHIPID_T210 0x21
/* Fuse registers */
#define FUSE_SKU_INFO 0x110
#define SKU_ODIN 0x83
/* Clock controller registers */
#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
@@ -110,7 +120,7 @@
#define CLKCHANGE_COMPLETE_INT (1 << 4)
#define EMC_DBG 0x8
#define EMC_DBG_READ_MUX_ACTIVE BIT(0)
#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
#define EMC_DBG_CFG_SWAP_ACTIVE_ONLY (0 << 26u)
#define EMC_DBG_CFG_SWAP_SWAP (1 << 26u)