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bdk: clock: remove non existent module ids

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And add comments to special handling ones
This commit is contained in:
CTCaer
2025-08-27 14:41:27 +03:00
parent c63ccd0cdc
commit b4b3133570
1 changed files with 123 additions and 171 deletions
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294
bdk/soc/clock.h
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@@ -469,109 +469,85 @@ typedef enum _clock_pto_id_t
enum CLK_L_DEV enum CLK_L_DEV
{ {
CLK_L_CPU = 0, // Only reset. Deprecated. CLK_L_CPU = 0, // Deprecated.
CLK_L_BPMP = 1, // Only reset. CLK_L_BPMP = 1, // Only reset.
CLK_L_SYS = 2, // Only reset. CLK_L_SYS = 2, // Only reset.
CLK_L_ISPB = 3, CLK_L_ISPB = 3,
CLK_L_RTC = 4, CLK_L_RTC = 4, // Only enable.
CLK_L_TMR = 5, CLK_L_TMR = 5,
CLK_L_UARTA = 6, CLK_L_UARTA = 6,
CLK_L_UARTB = 7, CLK_L_UARTB = 7,
CLK_L_GPIO = 8, CLK_L_GPIO = 8,
CLK_L_SDMMC2 = 9, CLK_L_SDMMC2 = 9,
CLK_L_SPDIF = 10, CLK_L_SPDIF = 10, // Only enable.
CLK_L_I2S2 = 11, // I2S1 CLK_L_I2S2 = 11, // Only enable.
CLK_L_I2C1 = 12, CLK_L_I2C1 = 12,
CLK_L_NDFLASH = 13, // HIDDEN. CLK_L_SDMMC1 = 14,
CLK_L_SDMMC1 = 14, CLK_L_SDMMC4 = 15,
CLK_L_SDMMC4 = 15, CLK_L_TWC = 16, // 3-Wire Controller. Deprecated.
CLK_L_TWC = 16, // HIDDEN. CLK_L_PWM = 17,
CLK_L_PWM = 17, CLK_L_I2S3 = 18, // Only enable.
CLK_L_I2S3 = 18, CLK_L_VI = 20,
CLK_L_EPP = 19, // HIDDEN. CLK_L_USBD = 22,
CLK_L_VI = 20, CLK_L_ISP = 23,
CLK_L_2D = 21, // HIDDEN. CLK_L_DISP2 = 26,
CLK_L_USBD = 22, CLK_L_DISP1 = 27,
CLK_L_ISP = 23, CLK_L_HOST1X = 28,
CLK_L_3D = 24, // HIDDEN. CLK_L_I2S1 = 30, // Only enable.
CLK_L_IDE = 25, // RESERVED. CLK_L_BPMP_CACHE_CTRL = 31, // Controller.
CLK_L_DISP2 = 26,
CLK_L_DISP1 = 27,
CLK_L_HOST1X = 28,
CLK_L_VCP = 29, // HIDDEN.
CLK_L_I2S1 = 30, // I2S0
CLK_L_BPMP_CACHE_CTRL = 31, // CONTROLLER
}; };
enum CLK_H_DEV enum CLK_H_DEV
{ {
CLK_H_MEM = 0, // MC. CLK_H_MEM = 0, // MC.
CLK_H_AHBDMA = 1, CLK_H_AHBDMA = 1,
CLK_H_APBDMA = 2, CLK_H_APBDMA = 2,
//CLK_H_ = 3, CLK_H_STAT_MON = 5,
CLK_H_KBC = 4, // HIDDEN. CLK_H_PMC = 6, // Only enable.
CLK_H_STAT_MON = 5, CLK_H_FUSE = 7,
CLK_H_PMC = 6, CLK_H_KFUSE = 8,
CLK_H_FUSE = 7, CLK_H_SPI1 = 9,
CLK_H_KFUSE = 8,
CLK_H_SPI1 = 9,
CLK_H_SNOR = 10, // HIDDEN.
CLK_H_JTAG2TBC = 11,
CLK_H_SPI2 = 12, CLK_H_SPI2 = 12,
CLK_H_XIO = 13, // HIDDEN. CLK_H_XIO = 13, // Misc IO. Deprecated?
CLK_H_SPI3 = 14, CLK_H_SPI3 = 14,
CLK_H_I2C5 = 15, CLK_H_I2C5 = 15,
CLK_H_DSI = 16, CLK_H_DSI = 16,
CLK_H_TVO = 17, // RESERVED.
CLK_H_HSI = 18, // HIDDEN.
CLK_H_HDMI = 19, // HIDDEN.
CLK_H_CSI = 20, CLK_H_CSI = 20,
CLK_H_TVDAC = 21, // RESERVED.
CLK_H_I2C2 = 22, CLK_H_I2C2 = 22,
CLK_H_UARTC = 23, CLK_H_UARTC = 23,
CLK_H_MIPI_CAL = 24, CLK_H_MIPI_CAL = 24,
CLK_H_EMC = 25, CLK_H_EMC = 25,
CLK_H_USB2 = 26, CLK_H_USB2 = 26,
CLK_H_USB3 = 27, // HIDDEN.
CLK_H_MPE = 28, // HIDDEN.
CLK_H_VDE = 29, // HIDDEN.
CLK_H_BSEA = 30, // HIDDEN.
CLK_H_BSEV = 31, CLK_H_BSEV = 31,
}; };
enum CLK_U_DEV enum CLK_U_DEV
{ {
CLK_U_SPEEDO = 0, // RESERVED. //CLK_U_SPEEDO = 0, // RESERVED. Old speedo ring oscillator.
CLK_U_UARTD = 1, CLK_U_UARTD = 1,
CLK_U_UARTE = 2, // HIDDEN. CLK_U_I2C3 = 3,
CLK_U_I2C3 = 3, CLK_U_SPI4 = 4,
CLK_U_SPI4 = 4, CLK_U_SDMMC3 = 5,
CLK_U_SDMMC3 = 5, CLK_U_PCIE = 6,
CLK_U_PCIE = 6, CLK_U_OWR = 7, // 1-Wire Controller. Deprecated.
CLK_U_OWR = 7, // RESERVED. CLK_U_AFI = 8,
CLK_U_AFI = 8, CLK_U_CSITE = 9,
CLK_U_CSITE = 9,
CLK_U_PCIEXCLK = 10, // Only reset. CLK_U_PCIEXCLK = 10, // Only reset.
CLK_U_BPMPUCQ = 11, // HIDDEN. CLK_U_LA = 12, // DFD.
CLK_U_LA = 12,
CLK_U_TRACECLKIN = 13, // HIDDEN.
CLK_U_SOC_THERM = 14, CLK_U_SOC_THERM = 14,
CLK_U_DTV = 15, CLK_U_DTV = 15, // Deprecated.
CLK_U_NAND_SPEED = 16, // HIDDEN.
CLK_U_I2C_SLOW = 17, CLK_U_I2C_SLOW = 17,
CLK_U_DSIB = 18, CLK_U_DSIB = 18,
CLK_U_TSEC = 19, CLK_U_TSEC = 19,
CLK_U_IRAMA = 20, CLK_U_IRAMA = 20, // Only enable.
CLK_U_IRAMB = 21, CLK_U_IRAMB = 21, // Only enable.
CLK_U_IRAMC = 22, CLK_U_IRAMC = 22, // Only enable.
CLK_U_IRAMD = 23, // EMUCIF ON RESET CLK_U_IRAMD = 23, // EMUCIF ON RESET
CLK_U_BPMP_CACHE_RAM = 24, CLK_U_BPMP_CACHE_RAM = 24, // Only enable.
CLK_U_XUSB_HOST = 25, CLK_U_XUSB_HOST = 25,
CLK_U_CLK_M_DOUBLER = 26, CLK_U_SUS_OUT = 28, // Only enable. VI MCLK. Deprecated?
CLK_U_MSENC = 27, // HIDDEN. CLK_U_DEV2_OUT = 29, // Only enable. DAP MCLK. Deprecated?
CLK_U_SUS_OUT = 28, CLK_U_DEV1_OUT = 30, // Only enable. DAP MCLK. Deprecated?
CLK_U_DEV2_OUT = 29,
CLK_U_DEV1_OUT = 30,
CLK_U_XUSB_DEV = 31, CLK_U_XUSB_DEV = 31,
}; };
@@ -579,133 +555,109 @@ enum CLK_V_DEV
{ {
CLK_V_CPUG = 0, CLK_V_CPUG = 0,
CLK_V_CPULP = 1, // Reserved. CLK_V_CPULP = 1, // Reserved.
CLK_V_3D2 = 2, // HIDDEN.
CLK_V_MSELECT = 3, CLK_V_MSELECT = 3,
CLK_V_TSENSOR = 4, CLK_V_TSENSOR = 4, // Only enable.
CLK_V_I2S4 = 5, CLK_V_I2S4 = 5, // Only enable.
CLK_V_I2S5 = 6, CLK_V_I2S5 = 6, // Only enable.
CLK_V_I2C4 = 7, CLK_V_I2C4 = 7,
CLK_V_SPI5 = 8, // HIDDEN. CLK_V_AHUB = 10, // AUDIO. Only enable.
CLK_V_SPI6 = 9, // HIDDEN. CLK_V_APB2APE = 11, // APBIF. Only enable.
CLK_V_AHUB = 10, // AUDIO.
CLK_V_APB2APE = 11, // APBIF.
CLK_V_DAM0 = 12, // HIDDEN.
CLK_V_DAM1 = 13, // HIDDEN.
CLK_V_DAM2 = 14, // HIDDEN.
CLK_V_HDA2CODEC_2X = 15, CLK_V_HDA2CODEC_2X = 15,
CLK_V_ATOMICS = 16, CLK_V_ATOMICS = 16,
//CLK_V_ = 17, CLK_V_SPDIF_DOUBLER = 22, // Only enable.
//CLK_V_ = 18,
//CLK_V_ = 19,
//CLK_V_ = 20,
//CLK_V_ = 21,
CLK_V_SPDIF_DOUBLER = 22,
CLK_V_ACTMON = 23, CLK_V_ACTMON = 23,
CLK_V_EXTPERIPH1 = 24, CLK_V_EXTPERIPH1 = 24,
CLK_V_EXTPERIPH2 = 25, CLK_V_EXTPERIPH2 = 25,
CLK_V_EXTPERIPH3 = 26, CLK_V_EXTPERIPH3 = 26,
CLK_V_SATA_OOB = 27, CLK_V_SATA_OOB = 27, // Only on T210.
CLK_V_SATA = 28, CLK_V_SATA = 28, // Only on T210.
CLK_V_HDA = 29, CLK_V_HDA = 29,
CLK_V_TZRAM = 30, // HIDDEN. CLK_V_TZRAM = 30,
CLK_V_SE = 31, // HIDDEN. CLK_V_SE = 31,
}; };
enum CLK_W_DEV enum CLK_W_DEV
{ {
CLK_W_HDA2HDMICODEC = 0, CLK_W_HDA2HDMICODEC = 0,
CLK_W_RESERVED0 = 1, //satacoldrstn CLK_W_SATACOLD = 1, // Enable reserved. Unused.
CLK_W_PCIERX0 = 2, CLK_W_PCIERX0 = 2, // Reset reserved.
CLK_W_PCIERX1 = 3, CLK_W_PCIERX1 = 3, // Reset reserved.
CLK_W_PCIERX2 = 4, CLK_W_PCIERX2 = 4, // Reset reserved.
CLK_W_PCIERX3 = 5, CLK_W_PCIERX3 = 5, // Reset reserved.
CLK_W_PCIERX4 = 6, CLK_W_PCIERX4 = 6, // Reset reserved.
CLK_W_PCIERX5 = 7, CLK_W_PCIERX5 = 7, // Reset reserved.
CLK_W_CEC = 8, CLK_W_CEC = 8,
CLK_W_PCIE2_IOBIST = 9, CLK_W_PCIE2_IOBIST = 9, // Reset reserved.
CLK_W_EMC_IOBIST = 10, CLK_W_EMC_IOBIST = 10, // Reset reserved.
CLK_W_HDMI_IOBIST = 11, // HIDDEN. CLK_W_SATA_IOBIST = 12, // Reset reserved.
CLK_W_SATA_IOBIST = 12, CLK_W_MIPI_IOBIST = 13, // Reset reserved.
CLK_W_MIPI_IOBIST = 13,
CLK_W_XUSB_PADCTL = 14, // Only reset. CLK_W_XUSB_PADCTL = 14, // Only reset.
CLK_W_XUSB = 15, CLK_W_XUSB = 15, // Only enable.
CLK_W_CILAB = 16, CLK_W_CILAB = 16, // Only enable.
CLK_W_CILCD = 17, CLK_W_CILCD = 17, // Only enable.
CLK_W_CILEF = 18, CLK_W_CILEF = 18, // Only enable.
CLK_W_DSIA_LP = 19, CLK_W_DSIA_LP = 19, // Only enable.
CLK_W_DSIB_LP = 20, CLK_W_DSIB_LP = 20, // Only enable.
CLK_W_ENTROPY = 21, CLK_W_ENTROPY = 21,
CLK_W_DDS = 22, // HIDDEN.
//CLK_W_ = 23,
CLK_W_DP2 = 24, // HIDDEN. CLK_W_DP2 = 24, // HIDDEN.
CLK_W_AMX0 = 25, // HIDDEN.
CLK_W_ADX0 = 26, // HIDDEN.
CLK_W_DVFS = 27, CLK_W_DVFS = 27,
CLK_W_XUSB_SS = 28, CLK_W_XUSB_SS = 28,
CLK_W_EMC_LATENCY = 29, CLK_W_EMC_LATENCY = 29, // Only enable.
CLK_W_MC1 = 30, CLK_W_MC1 = 30, // Only enable.
//CLK_W_ = 31,
}; };
enum CLK_X_DEV enum CLK_X_DEV
{ {
CLK_X_SPARE = 0, CLK_X_SPARE = 0,
CLK_X_DMIC1 = 1, CLK_X_DMIC1 = 1, // Only enable.
CLK_X_DMIC2 = 2, CLK_X_DMIC2 = 2, // Only enable.
CLK_X_ETR = 3, CLK_X_ETR = 3, // DFD.
CLK_X_CAM_MCLK = 4, CLK_X_CAM_MCLK = 4, // Only enable.
CLK_X_CAM_MCLK2 = 5, CLK_X_CAM_MCLK2 = 5, // Only enable.
CLK_X_I2C6 = 6, CLK_X_I2C6 = 6,
CLK_X_MC_CAPA = 7, // MC DAISY CHAIN1 CLK_X_MC_CAPA = 7, // MC Clients daisy chain 1. Only enable.
CLK_X_MC_CBPA = 8, // MC DAISY CHAIN2 CLK_X_MC_CBPA = 8, // MC Clients daisy chain 2. Only enable.
CLK_X_MC_CPU = 9, CLK_X_MC_CPU = 9, // MC CPU. Only enable.
CLK_X_MC_BBC = 10, CLK_X_MC_BBC = 10, // MC Backbone. Only enable.
CLK_X_VIM2_CLK = 11, CLK_X_VIM2_CLK = 11, // Only enable.
//CLK_X_ = 12, CLK_X_MIPIBIF = 13,
CLK_X_MIPIBIF = 13, //RESERVED CLK_X_EMC_DLL = 14, // Only enable.
CLK_X_EMC_DLL = 14, CLK_X_UART_FST_MIPI_CAL = 17, // Only enable.
//CLK_X_ = 15,
CLK_X_HDMI_AUDIO = 16, // HIDDEN.
CLK_X_UART_FST_MIPI_CAL = 17,
CLK_X_VIC = 18, CLK_X_VIC = 18,
//CLK_X_ = 19,
CLK_X_ADX1 = 20, // HIDDEN.
CLK_X_DPAUX = 21, CLK_X_DPAUX = 21,
CLK_X_SOR0 = 22, CLK_X_SOR0 = 22,
CLK_X_SOR1 = 23, CLK_X_SOR1 = 23,
CLK_X_GPU = 24, CLK_X_GPU = 24,
CLK_X_DBGAPB = 25, CLK_X_DBGAPB = 25, // Only enable.
CLK_X_HPLL_ADSP = 26, CLK_X_HPLL_ADSP = 26, // Only enable.
CLK_X_PLLP_ADSP = 27, CLK_X_PLLP_ADSP = 27, // Only enable.
CLK_X_PLLA_ADSP = 28, CLK_X_PLLA_ADSP = 28, // Only enable.
CLK_X_PLLG_REF = 29, CLK_X_PLLG_REF = 29, // Only enable.
//CLK_X_ = 30, CLK_X_EQOS = 30, // T210B01 only.
//CLK_X_ = 31,
}; };
enum CLK_Y_DEV enum CLK_Y_DEV
{ {
CLK_Y_SPARE1 = 0, CLK_Y_SPARE1 = 0,
CLK_Y_SDMMC_LEGACY_TM = 1, CLK_Y_SDMMC_LEGACY_TM = 1, // Only enable.
CLK_Y_NVDEC = 2, CLK_Y_NVDEC = 2,
CLK_Y_NVJPG = 3, CLK_Y_NVJPG = 3,
CLK_Y_AXIAP = 4, CLK_Y_AXIAP = 4, // DFD.
CLK_Y_DMIC3 = 5, CLK_Y_DMIC3 = 5, // Only enable.
CLK_Y_APE = 6, CLK_Y_APE = 6,
CLK_Y_ADSP = 7, CLK_Y_ADSP = 7,
CLK_Y_MC_CDPA = 8, // MC DAISY CHAIN4 CLK_Y_MC_CDPA = 8, // MC Clients daisy chain 4. Only enable.
CLK_Y_MC_CCPA = 9, // MC DAISY CHAIN3 CLK_Y_MC_CCPA = 9, // MC Clients daisy chain 3. Only enable.
CLK_Y_MAUD = 10, CLK_Y_MAUD = 10, // Only enable.
//CLK_Y_ = 11,
CLK_Y_SATA_USB_UPHY = 12, // Only reset. CLK_Y_SATA_USB_UPHY = 12, // Only reset.
CLK_Y_PEX_USB_UPHY = 13, // Only reset. CLK_Y_PEX_USB_UPHY = 13, // Only reset.
CLK_Y_TSECB = 14, CLK_Y_TSECB = 14,
CLK_Y_DPAUX1 = 15, CLK_Y_DPAUX1 = 15,
CLK_Y_VI_I2C = 16, CLK_Y_VI_I2C = 16,
CLK_Y_HSIC_TRK = 17, CLK_Y_HSIC_TRK = 17, // Only enable.
CLK_Y_USB2_TRK = 18, CLK_Y_USB2_TRK = 18, // Only enable.
CLK_Y_QSPI = 19, CLK_Y_QSPI = 19,
CLK_Y_UARTAPE = 20, CLK_Y_UARTAPE = 20, // Only enable.
CLK_Y_ADSPINTF = 21, // Only reset. CLK_Y_ADSPINTF = 21, // Only reset.
CLK_Y_ADSPPERIPH = 22, // Only reset. CLK_Y_ADSPPERIPH = 22, // Only reset.
CLK_Y_ADSPDBG = 23, // Only reset. CLK_Y_ADSPDBG = 23, // Only reset.
@@ -713,10 +665,10 @@ enum CLK_Y_DEV
CLK_Y_ADSPSCU = 25, // Only reset. CLK_Y_ADSPSCU = 25, // Only reset.
CLK_Y_ADSPNEON = 26, CLK_Y_ADSPNEON = 26,
CLK_Y_NVENC = 27, CLK_Y_NVENC = 27,
CLK_Y_IQC2 = 28, CLK_Y_IQC2 = 28, // Only enable. (Audio.)
CLK_Y_IQC1 = 29, CLK_Y_IQC1 = 29, // Only enable. (Audio.)
CLK_Y_SOR_SAFE = 30, CLK_Y_SOR_SAFE = 30, // Only enable.
CLK_Y_PLLP_OUT_CPU = 31, CLK_Y_PLLP_OUT_CPU = 31, // Only enable.
}; };
/*! Generic clock descriptor. */ /*! Generic clock descriptor. */