bdk: clock: use SET/CLR registers for all modules

This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.

bdk/soc/clock.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2024 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -171,6 +171,8 @@
 #define CLK_NO_SOURCE 0x0
 #define CLK_NOT_USED  0x0
 
+#define CLK_CLR_OFFSET 0x4
+
 /*! PLL control and status bits */
 #define PLL_BASE_LOCK        BIT(27)
 #define PLL_BASE_REF_DIS     BIT(29)
@@ -674,11 +676,11 @@ enum CLK_Y_DEV
 /*! Generic clock descriptor. */
 typedef struct _clk_rst_t
 {
-	u16 reset;
-	u16 enable;
+	u16 reset;  // Reset  SET.
+	u16 enable; // Enable SET.
 	u16 source;
-	u8 index;
-	u8 clk_src;
+	u8 index:5;
+	u8 clk_src:3;
 	u8 clk_div;
 } clk_rst_t;