diff --git a/bdk/mem/emc.h b/bdk/mem/emc.h
deleted file mode 100644
index a1b4c3a6..00000000
--- a/bdk/mem/emc.h
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra21_emc.h
- *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
- * Copyright (c) 2019-2024, CTCaer.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- *
- */
-
-#ifndef _EMC_H_
-#define _EMC_H_
-
-#define EMC_INTSTATUS 0x0
-#define EMC_DBG 0x8
-#define EMC_CFG 0xC
-#define EMC_CONFIG_SAMPLE_DELAY 0x5f0
-#define EMC_CFG_UPDATE 0x5f4
-#define EMC_ADR_CFG 0x10
-#define EMC_REFCTRL 0x20
-#define EMC_PIN 0x24
-#define EMC_TIMING_CONTROL 0x28
-#define EMC_RC 0x2c
-#define EMC_RFC 0x30
-#define EMC_RFCPB 0x590
-#define EMC_RAS 0x34
-#define EMC_RP 0x38
-#define EMC_R2W 0x3c
-#define EMC_W2R 0x40
-#define EMC_R2P 0x44
-#define EMC_W2P 0x48
-#define EMC_CCDMW 0x5c0
-#define EMC_RD_RCD 0x4c
-#define EMC_WR_RCD 0x50
-#define EMC_RRD 0x54
-#define EMC_REXT 0x58
-#define EMC_WDV 0x5c
-#define EMC_QUSE 0x60
-#define EMC_QRST 0x64
-#define EMC_ISSUE_QRST 0x428
-#define EMC_QSAFE 0x68
-#define EMC_RDV 0x6c
-#define EMC_REFRESH 0x70
-#define EMC_BURST_REFRESH_NUM 0x74
-#define EMC_PDEX2WR 0x78
-#define EMC_PDEX2RD 0x7c
-#define EMC_PDEX2CKE 0x118
-#define EMC_PCHG2PDEN 0x80
-#define EMC_ACT2PDEN 0x84
-#define EMC_AR2PDEN 0x88
-#define EMC_RW2PDEN 0x8c
-#define EMC_CKE2PDEN 0x11c
-#define EMC_TXSR 0x90
-#define EMC_TCKE 0x94
-#define EMC_TFAW 0x98
-#define EMC_TRPAB 0x9c
-#define EMC_TCLKSTABLE 0xa0
-#define EMC_TCLKSTOP 0xa4
-#define EMC_TREFBW 0xa8
-#define EMC_TPPD 0xac
-#define EMC_PDEX2MRR 0xb4
-#define EMC_ODT_WRITE 0xb0
-#define EMC_WEXT 0xb8
-#define EMC_CTT 0xBC
-#define EMC_RFC_SLR 0xc0
-#define EMC_MRS_WAIT_CNT2 0xc4
-#define EMC_MRS_WAIT_CNT 0xc8
-#define EMC_MRS 0xcc
-#define EMC_EMRS 0xd0
-#define EMC_REF 0xd4
-#define EMC_PRE 0xd8
-#define EMC_NOP 0xdc
-#define EMC_SELF_REF 0xe0
-#define EMC_DPD 0xe4
-#define EMC_MRW 0xe8
-#define EMC_MRR 0xec
-#define EMC_CMDQ 0xf0
-#define EMC_MC2EMCQ 0xf4
-#define EMC_FBIO_TWTM 0xF8
-#define EMC_FBIO_TRATM 0xFC
-#define EMC_FBIO_TWATM 0x108
-#define EMC_FBIO_TR2REF 0x10C
-#define EMC_FBIO_SPARE 0x100
-#define EMC_FBIO_CFG5 0x104
-#define EMC_FBIO_CFG6 0x114
-#define EMC_CFG_RSV 0x120
-#define EMC_ACPD_CONTROL 0x124
-#define EMC_MPC 0x128
-#define EMC_EMRS2 0x12c
-#define EMC_EMRS3 0x130
-#define EMC_MRW2 0x134
-#define EMC_MRW3 0x138
-#define EMC_MRW4 0x13c
-#define EMC_MRW5 0x4a0
-#define EMC_MRW6 0x4a4
-#define EMC_MRW7 0x4a8
-#define EMC_MRW8 0x4ac
-#define EMC_MRW9 0x4b0
-#define EMC_MRW10 0x4b4
-#define EMC_MRW11 0x4b8
-#define EMC_MRW12 0x4bc
-#define EMC_MRW13 0x4c0
-#define EMC_MRW14 0x4c4
-#define EMC_MRW15 0x4d0
-#define EMC_CFG_SYNC 0x4d4
-#define EMC_CLKEN_OVERRIDE 0x140
-#define EMC_R2R 0x144
-#define EMC_W2W 0x148
-#define EMC_EINPUT 0x14c
-#define EMC_EINPUT_DURATION 0x150
-#define EMC_PUTERM_EXTRA 0x154
-#define EMC_TCKESR 0x158
-#define EMC_TPD 0x15c
-#define EMC_STAT_CONTROL 0x160
-#define EMC_STAT_STATUS 0x164
-#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c
-#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0
-#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4
-#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8
-#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac
-#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0
-#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4
-#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8
-#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc
-#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0
-#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4
-#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8
-#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc
-#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0
-#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4
-#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218
-#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c
-#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220
-#define EMC_STAT_DRAM_DEV0_DSR 0x224
-#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228
-#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c
-#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230
-#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234
-#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238
-#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c
-#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240
-#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244
-#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248
-#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c
-#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250
-#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294
-#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298
-#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c
-#define EMC_STAT_DRAM_DEV1_DSR 0x2a0
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8
-#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc
-#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0
-#define EMC_STAT_DRAM_IO_DSR 0xcd4
-#define EMC_AUTO_CAL_CONFIG 0x2a4
-#define EMC_AUTO_CAL_CONFIG2 0x458
-#define EMC_AUTO_CAL_CONFIG3 0x45c
-#define EMC_AUTO_CAL_CONFIG4 0x5b0
-#define EMC_AUTO_CAL_CONFIG5 0x5b4
-#define EMC_AUTO_CAL_CONFIG6 0x5cc
-#define EMC_AUTO_CAL_CONFIG7 0x574
-#define EMC_AUTO_CAL_CONFIG8 0x2dc
-#define EMC_AUTO_CAL_CONFIG9 0x42C
-#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8
-#define EMC_AUTO_CAL_VREF_SEL_1 0x300
-#define EMC_AUTO_CAL_INTERVAL 0x2a8
-#define EMC_AUTO_CAL_STATUS 0x2ac
-#define EMC_AUTO_CAL_STATUS2 0x3d4
-#define EMC_AUTO_CAL_CHANNEL 0x464
-#define EMC_PMACRO_RX_TERM 0xc48
-#define EMC_PMACRO_DQ_TX_DRV 0xc70
-#define EMC_PMACRO_CA_TX_DRV 0xc74
-#define EMC_PMACRO_CMD_TX_DRV 0xc4c
-#define EMC_PMACRO_AUTOCAL_CFG_0 0x700
-#define EMC_PMACRO_AUTOCAL_CFG_1 0x704
-#define EMC_PMACRO_AUTOCAL_CFG_2 0x708
-#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78
-#define EMC_PMACRO_ZCTRL 0xc44
-#define EMC_XM2COMPPADCTRL 0x30c
-#define EMC_XM2COMPPADCTRL2 0x578
-#define EMC_XM2COMPPADCTRL3 0x2f4
-#define EMC_COMP_PAD_SW_CTRL 0x57c
-#define EMC_REQ_CTRL 0x2b0
-#define EMC_EMC_STATUS 0x2b4
-#define EMC_STATUS_MRR_DIVLD BIT(20)
-#define EMC_CFG_2 0x2b8
-#define EMC_CFG_DIG_DLL 0x2bc
-#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
-#define EMC_DIG_DLL_STATUS 0x2c4
-#define EMC_CFG_DIG_DLL_1 0x2c8
-#define EMC_RDV_MASK 0x2cc
-#define EMC_WDV_MASK 0x2d0
-#define EMC_RDV_EARLY_MASK 0x2d4
-#define EMC_RDV_EARLY 0x2d8
-#define EMC_WDV_CHK 0x4e0
-#define EMC_ZCAL_INTERVAL 0x2e0
-#define EMC_ZCAL_WAIT_CNT 0x2e4
-#define EMC_ZCAL_MRW_CMD 0x2e8
-#define EMC_ZQ_CAL 0x2ec
-#define EMC_SCRATCH0 0x324
-#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
-#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
-#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
-#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8
-#define EMC_SEL_DPD_CTRL 0x3d8
-#define EMC_FDPD_CTRL_DQ 0x310
-#define EMC_FDPD_CTRL_CMD 0x314
-#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
-#define EMC_REFCTRL2 0x580
-#define EMC_FBIO_CFG7 0x584
-#define EMC_DATA_BRLSHFT_0 0x588
-#define EMC_DATA_BRLSHFT_1 0x58c
-#define EMC_DQS_BRLSHFT_0 0x594
-#define EMC_DQS_BRLSHFT_1 0x598
-#define EMC_CMD_BRLSHFT_0 0x59c
-#define EMC_CMD_BRLSHFT_1 0x5a0
-#define EMC_CMD_BRLSHFT_2 0x5a4
-#define EMC_CMD_BRLSHFT_3 0x5a8
-#define EMC_QUSE_BRLSHFT_0 0x5ac
-#define EMC_QUSE_BRLSHFT_1 0x5b8
-#define EMC_QUSE_BRLSHFT_2 0x5bc
-#define EMC_QUSE_BRLSHFT_3 0x5c4
-#define EMC_FBIO_CFG8 0x5c8
-#define EMC_CMD_MAPPING_CMD0_0 0x380
-#define EMC_CMD_MAPPING_CMD0_1 0x384
-#define EMC_CMD_MAPPING_CMD0_2 0x388
-#define EMC_CMD_MAPPING_CMD1_0 0x38c
-#define EMC_CMD_MAPPING_CMD1_1 0x390
-#define EMC_CMD_MAPPING_CMD1_2 0x394
-#define EMC_CMD_MAPPING_CMD2_0 0x398
-#define EMC_CMD_MAPPING_CMD2_1 0x39c
-#define EMC_CMD_MAPPING_CMD2_2 0x3a0
-#define EMC_CMD_MAPPING_CMD3_0 0x3a4
-#define EMC_CMD_MAPPING_CMD3_1 0x3a8
-#define EMC_CMD_MAPPING_CMD3_2 0x3ac
-#define EMC_CMD_MAPPING_BYTE 0x3b0
-#define EMC_DYN_SELF_REF_CONTROL 0x3e0
-#define EMC_TXSRDLL 0x3e4
-#define EMC_CCFIFO_ADDR 0x3e8
-#define EMC_CCFIFO_DATA 0x3ec
-#define EMC_CCFIFO_STATUS 0x3f0
-#define EMC_SWIZZLE_RANK0_BYTE0 0x404
-#define EMC_SWIZZLE_RANK0_BYTE1 0x408
-#define EMC_SWIZZLE_RANK0_BYTE2 0x40c
-#define EMC_SWIZZLE_RANK0_BYTE3 0x410
-#define EMC_SWIZZLE_RANK1_BYTE0 0x418
-#define EMC_SWIZZLE_RANK1_BYTE1 0x41c
-#define EMC_SWIZZLE_RANK1_BYTE2 0x420
-#define EMC_SWIZZLE_RANK1_BYTE3 0x424
-#define EMC_TR_TIMING_0 0x3b4
-#define EMC_TR_CTRL_0 0x3b8
-#define EMC_TR_CTRL_1 0x3bc
-#define EMC_TR_DVFS 0x460
-#define EMC_SWITCH_BACK_CTRL 0x3c0
-#define EMC_TR_RDV 0x3c4
-#define EMC_TR_QPOP 0x3f4
-#define EMC_TR_RDV_MASK 0x3f8
-#define EMC_TR_QSAFE 0x3fc
-#define EMC_TR_QRST 0x400
-#define EMC_IBDLY 0x468
-#define EMC_OBDLY 0x46c
-#define EMC_TXDSRVTTGEN 0x480
-#define EMC_WE_DURATION 0x48c
-#define EMC_WS_DURATION 0x490
-#define EMC_WEV 0x494
-#define EMC_WSV 0x498
-#define EMC_CFG_3 0x49c
-#define EMC_CFG_PIPE_2 0x554
-#define EMC_CFG_PIPE_CLK 0x558
-#define EMC_CFG_PIPE_1 0x55c
-#define EMC_CFG_PIPE 0x560
-#define EMC_QPOP 0x564
-#define EMC_QUSE_WIDTH 0x568
-#define EMC_PUTERM_WIDTH 0x56c
-#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0
-#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4
-#define EMC_PROTOBIST_MISC 0x5d8
-#define EMC_PROTOBIST_WDATA_LOWER 0x5dc
-#define EMC_PROTOBIST_WDATA_UPPER 0x5e0
-#define EMC_PROTOBIST_RDATA 0x5ec
-#define EMC_DLL_CFG_0 0x5e4
-#define EMC_DLL_CFG_1 0x5e8
-#define EMC_TRAINING_CMD 0xe00
-#define EMC_TRAINING_CTRL 0xe04
-#define EMC_TRAINING_STATUS 0xe08
-#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c
-#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10
-#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14
-#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18
-#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c
-#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20
-#define EMC_TRAINING_READ_FINE_CTRL 0xe24
-#define EMC_TRAINING_READ_CTRL_MISC 0xe28
-#define EMC_TRAINING_READ_VREF_CTRL 0xe2c
-#define EMC_TRAINING_CA_FINE_CTRL 0xe30
-#define EMC_TRAINING_CA_CTRL_MISC 0xe34
-#define EMC_TRAINING_CA_CTRL_MISC1 0xe38
-#define EMC_TRAINING_CA_VREF_CTRL 0xe3c
-#define EMC_TRAINING_CA_TADR_CTRL 0xe40
-#define EMC_TRAINING_SETTLE 0xe44
-#define EMC_TRAINING_DEBUG_CTRL 0xe48
-#define EMC_TRAINING_DEBUG_DQ0 0xe4c
-#define EMC_TRAINING_DEBUG_DQ1 0xe50
-#define EMC_TRAINING_DEBUG_DQ2 0xe54
-#define EMC_TRAINING_DEBUG_DQ3 0xe58
-#define EMC_TRAINING_MPC 0xe5c
-#define EMC_TRAINING_PATRAM_CTRL 0xe60
-#define EMC_TRAINING_PATRAM_DQ 0xe64
-#define EMC_TRAINING_PATRAM_DMI 0xe68
-#define EMC_TRAINING_VREF_SETTLE 0xe6c
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c
-#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90
-#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4
-#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8
-#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc
-#define EMC_TRAINING_OPT_CA_VREF 0xec0
-#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4
-#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8
-#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc
-#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0
-#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4
-#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8
-#define EMC_TRAINING_DRAMC_TIMING 0xedc
-#define EMC_PMACRO_DATA_PI_CTRL 0x110
-#define EMC_PMACRO_CMD_PI_CTRL 0x114
-#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
-#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
-#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
-#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c
-#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
-#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
-#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
-#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
-#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
-#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c
-#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
-#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4
-#define EMC_PMACRO_TX_PWRD_0 0x720
-#define EMC_PMACRO_TX_PWRD_1 0x724
-#define EMC_PMACRO_TX_PWRD_2 0x728
-#define EMC_PMACRO_TX_PWRD_3 0x72c
-#define EMC_PMACRO_TX_PWRD_4 0x730
-#define EMC_PMACRO_TX_PWRD_5 0x734
-#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
-#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
-#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c
-#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
-#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
-#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
-#define EMC_PMACRO_DDLL_BYPASS 0x760
-#define EMC_PMACRO_DDLL_PWRD_0 0x770
-#define EMC_PMACRO_DDLL_PWRD_1 0x774
-#define EMC_PMACRO_DDLL_PWRD_2 0x778
-#define EMC_PMACRO_CMD_CTRL_0 0x780
-#define EMC_PMACRO_CMD_CTRL_1 0x784
-#define EMC_PMACRO_CMD_CTRL_2 0x788
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8
-#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0
-#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4
-#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8
-#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0
-#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4
-#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8
-#define EMC_PMACRO_IB_RXRT 0xcf4
-#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00
-#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04
-#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08
-#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c
-#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10
-#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14
-#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20
-#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24
-#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28
-#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30
-#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34
-#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38
-#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0
-#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c
-#define EMC_PMACRO_PAD_CFG_CTRL 0xc40
-#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50
-#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54
-#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58
-#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c
-#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
-#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
-#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
-#define EMC_PMACRO_DSR_VTTGEN_CTRL0 0xC6C
-#define EMC_PMACRO_BRICK_MAPPING_0 0xc80
-#define EMC_PMACRO_BRICK_MAPPING_1 0xc84
-#define EMC_PMACRO_BRICK_MAPPING_2 0xc88
-#define EMC_PMACRO_DDLLCAL_CAL 0xce0
-#define EMC_PMACRO_DDLL_OFFSET 0xce4
-#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8
-#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
-#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
-#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
-#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
-#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
-#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xD40
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xD44
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xD48
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xD4C
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xD50
-#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xD54
-#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xD60
-#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xD64
-#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xD68
-#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xD6C
-#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xD70
-#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xD74
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xD80
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xD84
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xD88
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xD8C
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xD90
-#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xD94
-#define EMC_PMC_SCRATCH1 0x440
-#define EMC_PMC_SCRATCH2 0x444
-#define EMC_PMC_SCRATCH3 0x448
-
-#define EMC_STATUS_UPDATE_TIMEOUT 1000
-
-typedef enum _emc_mr_t
-{
- MR0_FEAT = 0,
- MR4_TEMP = 4,
- MR5_MAN_ID = 5,
- MR6_REV_ID1 = 6,
- MR7_REV_ID2 = 7,
- MR8_DENSITY = 8,
-} emc_mr_t;
-
-enum
-{
- EMC_CHAN0 = 0,
- EMC_CHAN1 = 1
-};
-
-typedef struct _emc_mr_chip_data_t
-{
- // Device 0.
- u8 rank0_ch0;
- u8 rank0_ch1;
-
- // Device 1.
- u8 rank1_ch0;
- u8 rank1_ch1;
-} emc_mr_chip_data_t;
-
-typedef struct _emc_mr_data_t
-{
- emc_mr_chip_data_t chip0;
- emc_mr_chip_data_t chip1;
-} emc_mr_data_t;
-
-#endif
diff --git a/bdk/mem/emc_t210.h b/bdk/mem/emc_t210.h
new file mode 100644
index 00000000..882b450b
--- /dev/null
+++ b/bdk/mem/emc_t210.h
@@ -0,0 +1,1528 @@
+/*
+ * Copyright (c) 2019-2025 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _EMC_T210_H_
+#define _EMC_T210_H_
+
+/* External Memory Controller registers */
+#define EMC_INTSTATUS 0x0
+#define EMC_INTMASK 0x4
+#define EMC_DBG 0x8
+#define EMC_CFG 0xC
+#define EMC_ADR_CFG 0x10
+#define EMC_REFCTRL 0x20
+#define EMC_PIN 0x24
+#define EMC_TIMING_CONTROL 0x28
+#define EMC_RC 0x2C
+#define EMC_RFC 0x30
+#define EMC_RAS 0x34
+#define EMC_RP 0x38
+#define EMC_R2W 0x3C
+#define EMC_W2R 0x40
+#define EMC_R2P 0x44
+#define EMC_W2P 0x48
+#define EMC_RD_RCD 0x4C
+#define EMC_WR_RCD 0x50
+#define EMC_RRD 0x54
+#define EMC_REXT 0x58
+#define EMC_WDV 0x5C
+#define EMC_QUSE 0x60
+#define EMC_QRST 0x64
+#define EMC_QSAFE 0x68
+#define EMC_RDV 0x6C
+#define EMC_REFRESH 0x70
+#define EMC_BURST_REFRESH_NUM 0x74
+#define EMC_PDEX2WR 0x78
+#define EMC_PDEX2RD 0x7C
+#define EMC_PCHG2PDEN 0x80
+#define EMC_ACT2PDEN 0x84
+#define EMC_AR2PDEN 0x88
+#define EMC_RW2PDEN 0x8C
+#define EMC_TXSR 0x90
+#define EMC_TCKE 0x94
+#define EMC_TFAW 0x98
+#define EMC_TRPAB 0x9C
+#define EMC_TCLKSTABLE 0xA0
+#define EMC_TCLKSTOP 0xA4
+#define EMC_TREFBW 0xA8
+#define EMC_TPPD 0xAC
+#define EMC_ODT_WRITE 0xB0
+#define EMC_PDEX2MRR 0xB4
+#define EMC_WEXT 0xB8
+#define EMC_RFC_SLR 0xC0
+#define EMC_MRS_WAIT_CNT2 0xC4
+#define EMC_MRS_WAIT_CNT 0xC8
+#define EMC_MRS 0xCC
+#define EMC_EMRS 0xD0
+#define EMC_REF 0xD4
+#define EMC_PRE 0xD8
+#define EMC_NOP 0xDC
+#define EMC_SELF_REF 0xE0
+#define EMC_DPD 0xE4
+#define EMC_MRW 0xE8
+#define EMC_MRR 0xEC
+#define EMC_CMDQ 0xF0
+#define EMC_MC2EMCQ 0xF4
+#define EMC_FBIO_SPARE 0x100
+#define EMC_FBIO_CFG5 0x104
+#define EMC_PDEX2CKE 0x118
+#define EMC_CKE2PDEN 0x11C
+#define EMC_CFG_RSV 0x120
+#define EMC_ACPD_CONTROL 0x124
+#define EMC_MPC 0x128
+#define EMC_EMRS2 0x12C
+#define EMC_EMRS3 0x130
+#define EMC_MRW2 0x134
+#define EMC_MRW3 0x138
+#define EMC_MRW4 0x13C
+#define EMC_CLKEN_OVERRIDE 0x140
+#define EMC_R2R 0x144
+#define EMC_W2W 0x148
+#define EMC_EINPUT 0x14C
+#define EMC_EINPUT_DURATION 0x150
+#define EMC_PUTERM_EXTRA 0x154
+#define EMC_TCKESR 0x158
+#define EMC_TPD 0x15C
+#define EMC_STAT_CONTROL 0x160
+#define EMC_STAT_STATUS 0x164
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19C
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1A0
+#define EMC_STAT_DRAM_CLOCKS_LO 0x1A4
+#define EMC_STAT_DRAM_CLOCKS_HI 0x1A8
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1AC
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1B0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1B4
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1B8
+#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1BC
+#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1C0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1C4
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1C8
+#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1CC
+#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1D0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1D4
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1D8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1DC
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1E0
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1E4
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1E8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1EC
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1F0
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1F4
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1F8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1FC
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20C
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218
+#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21C
+#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220
+#define EMC_STAT_DRAM_DEV0_DSR 0x224
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22C
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234
+#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238
+#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23C
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244
+#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248
+#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24C
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25C
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26C
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27C
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28C
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294
+#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298
+#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29C
+#define EMC_STAT_DRAM_DEV1_DSR 0x2A0
+#define EMC_AUTO_CAL_CONFIG 0x2A4
+#define EMC_AUTO_CAL_INTERVAL 0x2A8
+#define EMC_AUTO_CAL_STATUS 0x2AC
+#define EMC_REQ_CTRL 0x2B0
+#define EMC_EMC_STATUS 0x2B4
+#define EMC_STATUS_MRR_DIVLD BIT(20)
+#define EMC_CFG_2 0x2B8
+#define EMC_CFG_DIG_DLL 0x2BC
+#define EMC_CFG_DIG_DLL_PERIOD 0x2C0
+#define EMC_DIG_DLL_STATUS 0x2C4
+#define EMC_CFG_DIG_DLL_1 0x2C8
+#define EMC_RDV_MASK 0x2CC
+#define EMC_WDV_MASK 0x2D0
+#define EMC_RDV_EARLY_MASK 0x2D4
+#define EMC_RDV_EARLY 0x2D8
+#define EMC_AUTO_CAL_CONFIG8 0x2DC
+#define EMC_ZCAL_INTERVAL 0x2E0
+#define EMC_ZCAL_WAIT_CNT 0x2E4
+#define EMC_ZCAL_MRW_CMD 0x2E8
+#define EMC_ZQ_CAL 0x2EC
+#define EMC_XM2COMPPADCTRL3 0x2F4
+#define EMC_AUTO_CAL_VREF_SEL_0 0x2F8
+#define EMC_AUTO_CAL_VREF_SEL_1 0x300
+#define EMC_XM2COMPPADCTRL 0x30C
+#define EMC_FDPD_CTRL_DQ 0x310
+#define EMC_FDPD_CTRL_CMD 0x314
+#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
+#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31C
+#define EMC_SCRATCH0 0x324
+#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
+#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
+#define EMC_CMD_MAPPING_CMD0_0 0x380
+#define EMC_CMD_MAPPING_CMD0_1 0x384
+#define EMC_CMD_MAPPING_CMD0_2 0x388
+#define EMC_CMD_MAPPING_CMD1_0 0x38C
+#define EMC_CMD_MAPPING_CMD1_1 0x390
+#define EMC_CMD_MAPPING_CMD1_2 0x394
+#define EMC_CMD_MAPPING_CMD2_0 0x398
+#define EMC_CMD_MAPPING_CMD2_1 0x39C
+#define EMC_CMD_MAPPING_CMD2_2 0x3A0
+#define EMC_CMD_MAPPING_CMD3_0 0x3A4
+#define EMC_CMD_MAPPING_CMD3_1 0x3A8
+#define EMC_CMD_MAPPING_CMD3_2 0x3AC
+#define EMC_CMD_MAPPING_BYTE 0x3B0
+#define EMC_TR_TIMING_0 0x3B4
+#define EMC_TR_CTRL_0 0x3B8
+#define EMC_TR_CTRL_1 0x3BC
+#define EMC_SWITCH_BACK_CTRL 0x3C0
+#define EMC_TR_RDV 0x3C4
+#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3C8
+#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC
+#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3D0
+#define EMC_AUTO_CAL_STATUS2 0x3D4
+#define EMC_SEL_DPD_CTRL 0x3D8
+#define EMC_PRE_REFRESH_REQ_CNT 0x3DC
+#define EMC_DYN_SELF_REF_CONTROL 0x3E0
+#define EMC_TXSRDLL 0x3E4
+#define EMC_CCFIFO_ADDR 0x3E8
+#define EMC_CCFIFO_DATA 0x3EC
+#define EMC_CCFIFO_STATUS 0x3F0
+#define EMC_TR_QPOP 0x3F4
+#define EMC_TR_RDV_MASK 0x3F8
+#define EMC_TR_QSAFE 0x3FC
+#define EMC_TR_QRST 0x400
+#define EMC_SWIZZLE_RANK0_BYTE0 0x404
+#define EMC_SWIZZLE_RANK0_BYTE1 0x408
+#define EMC_SWIZZLE_RANK0_BYTE2 0x40C
+#define EMC_SWIZZLE_RANK0_BYTE3 0x410
+#define EMC_SWIZZLE_RANK1_BYTE0 0x418
+#define EMC_SWIZZLE_RANK1_BYTE1 0x41C
+#define EMC_SWIZZLE_RANK1_BYTE2 0x420
+#define EMC_SWIZZLE_RANK1_BYTE3 0x424
+#define EMC_ISSUE_QRST 0x428
+#define EMC_PMC_SCRATCH1 0x440
+#define EMC_PMC_SCRATCH2 0x444
+#define EMC_PMC_SCRATCH3 0x448
+#define EMC_AUTO_CAL_CONFIG2 0x458
+#define EMC_AUTO_CAL_CONFIG3 0x45C
+#define EMC_TR_DVFS 0x460
+#define EMC_AUTO_CAL_CHANNEL 0x464
+#define EMC_IBDLY 0x468
+#define EMC_OBDLY 0x46C
+#define EMC_TXDSRVTTGEN 0x480
+#define EMC_WE_DURATION 0x48C
+#define EMC_WS_DURATION 0x490
+#define EMC_WEV 0x494
+#define EMC_WSV 0x498
+#define EMC_CFG_3 0x49C
+#define EMC_MRW5 0x4A0
+#define EMC_MRW6 0x4A4
+#define EMC_MRW7 0x4A8
+#define EMC_MRW8 0x4AC
+#define EMC_MRW9 0x4B0
+#define EMC_MRW10 0x4B4
+#define EMC_MRW11 0x4B8
+#define EMC_MRW12 0x4BC
+#define EMC_MRW13 0x4C0
+#define EMC_MRW14 0x4C4
+#define EMC_MRW15 0x4D0
+#define EMC_CFG_SYNC 0x4D4
+#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8
+#define EMC_WDV_CHK 0x4E0
+#define EMC_CFG_PIPE_2 0x554
+#define EMC_CFG_PIPE_CLK 0x558
+#define EMC_CFG_PIPE_1 0x55C
+#define EMC_CFG_PIPE 0x560
+#define EMC_QPOP 0x564
+#define EMC_QUSE_WIDTH 0x568
+#define EMC_PUTERM_WIDTH 0x56C
+#define EMC_AUTO_CAL_CONFIG7 0x574
+#define EMC_XM2COMPPADCTRL2 0x578
+#define EMC_COMP_PAD_SW_CTRL 0x57C
+#define EMC_REFCTRL2 0x580
+#define EMC_FBIO_CFG7 0x584
+#define EMC_DATA_BRLSHFT_0 0x588
+#define EMC_DATA_BRLSHFT_1 0x58C
+#define EMC_RFCPB 0x590
+#define EMC_DQS_BRLSHFT_0 0x594
+#define EMC_DQS_BRLSHFT_1 0x598
+#define EMC_CMD_BRLSHFT_0 0x59C
+#define EMC_CMD_BRLSHFT_1 0x5A0
+#define EMC_CMD_BRLSHFT_2 0x5A4
+#define EMC_CMD_BRLSHFT_3 0x5A8
+#define EMC_QUSE_BRLSHFT_0 0x5AC
+#define EMC_AUTO_CAL_CONFIG4 0x5B0
+#define EMC_AUTO_CAL_CONFIG5 0x5B4
+#define EMC_QUSE_BRLSHFT_1 0x5B8
+#define EMC_QUSE_BRLSHFT_2 0x5BC
+#define EMC_CCDMW 0x5C0
+#define EMC_QUSE_BRLSHFT_3 0x5C4
+#define EMC_FBIO_CFG8 0x5C8
+#define EMC_AUTO_CAL_CONFIG6 0x5CC
+#define EMC_PROTOBIST_CONFIG_ADR_1 0x5D0
+#define EMC_PROTOBIST_CONFIG_ADR_2 0x5D4
+#define EMC_PROTOBIST_MISC 0x5D8
+#define EMC_PROTOBIST_WDATA_LOWER 0x5DC
+#define EMC_PROTOBIST_WDATA_UPPER 0x5E0
+#define EMC_DLL_CFG_0 0x5E4
+#define EMC_DLL_CFG_1 0x5E8
+#define EMC_PROTOBIST_RDATA 0x5EC
+#define EMC_CONFIG_SAMPLE_DELAY 0x5F0
+#define EMC_CFG_UPDATE 0x5F4
+#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
+#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
+#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
+#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C
+#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
+#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
+#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
+#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
+#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
+#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C
+#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
+#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68C
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6A0
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6A4
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6A8
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6AC
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6B0
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6B4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6D0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6D4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6F0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6F4
+#define EMC_PMACRO_AUTOCAL_CFG_0 0x700
+#define EMC_PMACRO_AUTOCAL_CFG_1 0x704
+#define EMC_PMACRO_AUTOCAL_CFG_2 0x708
+#define EMC_PMACRO_TX_PWRD_0 0x720
+#define EMC_PMACRO_TX_PWRD_1 0x724
+#define EMC_PMACRO_TX_PWRD_2 0x728
+#define EMC_PMACRO_TX_PWRD_3 0x72C
+#define EMC_PMACRO_TX_PWRD_4 0x730
+#define EMC_PMACRO_TX_PWRD_5 0x734
+#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
+#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
+#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
+#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74C
+#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
+#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
+#define EMC_PMACRO_DDLL_BYPASS 0x760
+#define EMC_PMACRO_DDLL_PWRD_0 0x770
+#define EMC_PMACRO_DDLL_PWRD_1 0x774
+#define EMC_PMACRO_DDLL_PWRD_2 0x778
+#define EMC_PMACRO_CMD_CTRL_0 0x780
+#define EMC_PMACRO_CMD_CTRL_1 0x784
+#define EMC_PMACRO_CMD_CTRL_2 0x788
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8AC
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8BC
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99C
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9A0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9A4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9A8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9AC
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9B0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9B4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9B8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9BC
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xA80
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xA84
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xA88
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xA90
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xA94
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xA98
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xAA0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xAA4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xAA8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xAB0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xAB4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xAB8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xB80
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xB84
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xB88
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xB90
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xB94
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xB98
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xBA0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xBA4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xBA8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xBB0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xBB4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xBB8
+#define EMC_PMACRO_IB_VREF_DQ_0 0xBE0
+#define EMC_PMACRO_IB_VREF_DQ_1 0xBE4
+#define EMC_PMACRO_IB_VREF_DQ_2 0xBE8
+#define EMC_PMACRO_IB_VREF_DQS_0 0xBF0
+#define EMC_PMACRO_IB_VREF_DQS_1 0xBF4
+#define EMC_PMACRO_IB_VREF_DQS_2 0xBF8
+#define EMC_PMACRO_DDLL_LONG_CMD_0 0xC00
+#define EMC_PMACRO_DDLL_LONG_CMD_1 0xC04
+#define EMC_PMACRO_DDLL_LONG_CMD_2 0xC08
+#define EMC_PMACRO_DDLL_LONG_CMD_3 0xC0C
+#define EMC_PMACRO_DDLL_LONG_CMD_4 0xC10
+#define EMC_PMACRO_DDLL_LONG_CMD_5 0xC14
+#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xC20
+#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xC24
+#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xC28
+#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30
+#define EMC_PMACRO_VTTGEN_CTRL_0 0xC34
+#define EMC_PMACRO_VTTGEN_CTRL_1 0xC38
+#define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C
+#define EMC_PMACRO_PAD_CFG_CTRL 0xC40
+#define EMC_PMACRO_ZCTRL 0xC44
+#define EMC_PMACRO_RX_TERM 0xC48
+#define EMC_PMACRO_CMD_TX_DRV 0xC4C
+#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xC50
+#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xC54
+#define EMC_PMACRO_CMD_RX_TERM_MODE 0xC58
+#define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C
+#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60
+#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64
+#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68 // Only in T210.
+#define EMC_PMACRO_DQ_TX_DRV 0xC70
+#define EMC_PMACRO_CA_TX_DRV 0xC74
+#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78
+#define EMC_PMACRO_BRICK_MAPPING_0 0xC80
+#define EMC_PMACRO_BRICK_MAPPING_1 0xC84
+#define EMC_PMACRO_BRICK_MAPPING_2 0xC88
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xC8C
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xC90
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xC94
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xC98
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xC9C
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xCA0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xCA4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xCA8
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xCAC
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xCB0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xCB4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xCB8
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xCBC
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xCC0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xCC4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xCC8
+#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xCCC
+#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xCD0
+#define EMC_STAT_DRAM_IO_DSR 0xCD4
+#define EMC_PMACRO_DDLLCAL_CAL 0xCE0 // Only in T210.
+#define EMC_PMACRO_DDLL_OFFSET 0xCE4
+#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xCE8
+#define EMC_PMACRO_VTTGEN_CTRL_2 0xCF0
+#define EMC_PMACRO_IB_RXRT 0xCF4
+#define EMC_PMACRO_TRAINING_CTRL_0 0xCF8
+#define EMC_PMACRO_TRAINING_CTRL_1 0xCFC
+#define EMC_TRAINING_CMD 0xE00
+#define EMC_TRAINING_CTRL 0xE04
+#define EMC_TRAINING_STATUS 0xE08
+#define EMC_TRAINING_QUSE_CORS_CTRL 0xE0C
+#define EMC_TRAINING_QUSE_FINE_CTRL 0xE10
+#define EMC_TRAINING_QUSE_CTRL_MISC 0xE14
+#define EMC_TRAINING_WRITE_FINE_CTRL 0xE18
+#define EMC_TRAINING_WRITE_CTRL_MISC 0xE1C
+#define EMC_TRAINING_WRITE_VREF_CTRL 0xE20
+#define EMC_TRAINING_READ_FINE_CTRL 0xE24
+#define EMC_TRAINING_READ_CTRL_MISC 0xE28
+#define EMC_TRAINING_READ_VREF_CTRL 0xE2C
+#define EMC_TRAINING_CA_FINE_CTRL 0xE30
+#define EMC_TRAINING_CA_CTRL_MISC 0xE34
+#define EMC_TRAINING_CA_CTRL_MISC1 0xE38
+#define EMC_TRAINING_CA_VREF_CTRL 0xE3C
+#define EMC_TRAINING_CA_TADR_CTRL 0xE40
+#define EMC_TRAINING_SETTLE 0xE44
+#define EMC_TRAINING_DEBUG_CTRL 0xE48
+#define EMC_TRAINING_DEBUG_DQ0 0xE4C
+#define EMC_TRAINING_DEBUG_DQ1 0xE50
+#define EMC_TRAINING_DEBUG_DQ2 0xE54
+#define EMC_TRAINING_DEBUG_DQ3 0xE58
+#define EMC_TRAINING_MPC 0xE5C
+#define EMC_TRAINING_PATRAM_CTRL 0xE60
+#define EMC_TRAINING_PATRAM_DQ 0xE64
+#define EMC_TRAINING_PATRAM_DMI 0xE68
+#define EMC_TRAINING_VREF_SETTLE 0xE6C
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xE70
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xE74
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xE78
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xE7C
+#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xE80
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xE84
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xE88
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xE8C
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xE90
+#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xE94
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xE98
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xE9C
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xEA0
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xEA4
+#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xEA8
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xEAC
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xEB0
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xEB4
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xEB8
+#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xEBC
+#define EMC_TRAINING_OPT_CA_VREF 0xEC0
+#define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4
+#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xEC8
+#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xECC
+#define EMC_TRAINING_QUSE_VREF_CTRL 0xED0
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8
+#define EMC_TRAINING_DRAMC_TIMING 0xEDC
+
+/* T210B01 only registers */
+#define EMC_TRTM_B01 0xBC
+#define EMC_TWTM_B01 0xF8
+#define EMC_TRATM_B01 0xFC
+#define EMC_TWATM_B01 0x108
+#define EMC_TR2REF_B01 0x10C
+#define EMC_PMACRO_DATA_PI_CTRL_B01 0x110
+#define EMC_PMACRO_CMD_PI_CTRL_B01 0x114
+#define EMC_PMACRO_PMU_CTRL_B01 0x304
+#define EMC_PMACRO_XM2COMP_PMU_CTRL_B01 0x308
+#define EMC_AUTO_CAL_CONFIG9_B01 0x42C
+#define EMC_PMACRO_DDLLCAL_EN_B01 0x44C
+#define EMC_PMACRO_DLL_CFG_0_B01 0x5E4
+#define EMC_PMACRO_DLL_CFG_1_B01 0x5E8
+#define EMC_PMACRO_DLL_CFG_2_B01 0x5F8
+#define EMC_PMACRO_DSR_VTTGEN_CTRL_0_B01 0xC6C
+#define EMC_PMACRO_DDLLCAL_CAL_0_B01 0xD00
+#define EMC_PMACRO_DDLLCAL_CAL_1_B01 0xD04
+#define EMC_PMACRO_DDLLCAL_CAL_2_B01 0xD08
+#define EMC_PMACRO_DDLLCAL_CAL_3_B01 0xD0C
+#define EMC_PMACRO_DDLLCAL_CAL_4_B01 0xD10
+#define EMC_PMACRO_DDLLCAL_CAL_5_B01 0xD14
+#define EMC_PMACRO_DIG_DLL_STATUS_0_B01 0xD20
+#define EMC_PMACRO_DIG_DLL_STATUS_1_B01 0xD24
+#define EMC_PMACRO_DIG_DLL_STATUS_2_B01 0xD28
+#define EMC_PMACRO_DIG_DLL_STATUS_3_B01 0xD2C
+#define EMC_PMACRO_DIG_DLL_STATUS_4_B01 0xD30
+#define EMC_PMACRO_DIG_DLL_STATUS_5_B01 0xD34
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_0_B01 0xD40
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_1_B01 0xD44
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_2_B01 0xD48
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_3_B01 0xD4C
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_4_B01 0xD50
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_5_B01 0xD54
+#define EMC_PMACRO_PERBIT_RFU_CTRL_0_B01 0xD60
+#define EMC_PMACRO_PERBIT_RFU_CTRL_1_B01 0xD64
+#define EMC_PMACRO_PERBIT_RFU_CTRL_2_B01 0xD68
+#define EMC_PMACRO_PERBIT_RFU_CTRL_3_B01 0xD6C
+#define EMC_PMACRO_PERBIT_RFU_CTRL_4_B01 0xD70
+#define EMC_PMACRO_PERBIT_RFU_CTRL_5_B01 0xD74
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_0_B01 0xD80
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_1_B01 0xD84
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_2_B01 0xD88
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_3_B01 0xD8C
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_4_B01 0xD90
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_5_B01 0xD94
+#define EMC_PMACRO_PMU_OUT_EOFF1_0_B01 0xDA0
+#define EMC_PMACRO_PMU_OUT_EOFF1_1_B01 0xDA4
+#define EMC_PMACRO_PMU_OUT_EOFF1_2_B01 0xDA8
+#define EMC_PMACRO_PMU_OUT_EOFF1_3_B01 0xDAC
+#define EMC_PMACRO_PMU_OUT_EOFF1_4_B01 0xDB0
+#define EMC_PMACRO_PMU_OUT_EOFF1_5_B01 0xDB4
+#define EMC_PMACRO_COMP_PMU_OUT_B01 0xDC0
+
+#define EMC_STATUS_UPDATE_TIMEOUT 1000
+
+typedef enum _emc_mr_t
+{
+ MR0_FEAT = 0,
+ MR4_TEMP = 4,
+ MR5_MAN_ID = 5,
+ MR6_REV_ID1 = 6,
+ MR7_REV_ID2 = 7,
+ MR8_DENSITY = 8,
+} emc_mr_t;
+
+enum
+{
+ EMC_CHAN0 = 0,
+ EMC_CHAN1 = 1
+};
+
+typedef struct _emc_mr_chip_data_t
+{
+ // Device 0.
+ u8 rank0_ch0;
+ u8 rank0_ch1;
+
+ // Device 1.
+ u8 rank1_ch0;
+ u8 rank1_ch1;
+} emc_mr_chip_data_t;
+
+typedef struct _emc_mr_data_t
+{
+ emc_mr_chip_data_t chip0;
+ emc_mr_chip_data_t chip1;
+} emc_mr_data_t;
+
+typedef struct _emc_regs_t210_t {
+/* 0x000 */ u32 emc_intstatus;
+/* 0x004 */ u32 emc_intmask;
+/* 0x008 */ u32 emc_dbg;
+/* 0x00c */ u32 emc_cfg;
+/* 0x010 */ u32 emc_adr_cfg;
+/* 0x014 */ u32 emc_rsvd_14[3];
+/* 0x020 */ u32 emc_refctrl;
+/* 0x024 */ u32 emc_pin;
+/* 0x028 */ u32 emc_timing_control;
+/* 0x02c */ u32 emc_rc;
+/* 0x030 */ u32 emc_rfc;
+/* 0x034 */ u32 emc_ras;
+/* 0x038 */ u32 emc_rp;
+/* 0x03c */ u32 emc_r2w;
+/* 0x040 */ u32 emc_w2r;
+/* 0x044 */ u32 emc_r2p;
+/* 0x048 */ u32 emc_w2p;
+/* 0x04c */ u32 emc_rd_rcd;
+/* 0x050 */ u32 emc_wr_rcd;
+/* 0x054 */ u32 emc_rrd;
+/* 0x058 */ u32 emc_rext;
+/* 0x05c */ u32 emc_wdv;
+/* 0x060 */ u32 emc_quse;
+/* 0x064 */ u32 emc_qrst;
+/* 0x068 */ u32 emc_qsafe;
+/* 0x06c */ u32 emc_rdv;
+/* 0x070 */ u32 emc_refresh;
+/* 0x074 */ u32 emc_burst_refresh_num;
+/* 0x078 */ u32 emc_pdex2wr;
+/* 0x07c */ u32 emc_pdex2rd;
+/* 0x080 */ u32 emc_pchg2pden;
+/* 0x084 */ u32 emc_act2pden;
+/* 0x088 */ u32 emc_ar2pden;
+/* 0x08c */ u32 emc_rw2pden;
+/* 0x090 */ u32 emc_txsr;
+/* 0x094 */ u32 emc_tcke;
+/* 0x098 */ u32 emc_tfaw;
+/* 0x09c */ u32 emc_trpab;
+/* 0x0a0 */ u32 emc_tclkstable;
+/* 0x0a4 */ u32 emc_tclkstop;
+/* 0x0a8 */ u32 emc_trefbw;
+/* 0x0ac */ u32 emc_tppd;
+/* 0x0b0 */ u32 emc_odt_write;
+/* 0x0b4 */ u32 emc_pdex2mrr;
+/* 0x0b8 */ u32 emc_wext;
+/* 0x0bc */ u32 emc_trtm_b01;
+/* 0x0c0 */ u32 emc_rfc_slr;
+/* 0x0c4 */ u32 emc_mrs_wait_cnt2;
+/* 0x0c8 */ u32 emc_mrs_wait_cnt;
+/* 0x0cc */ u32 emc_mrs;
+/* 0x0d0 */ u32 emc_emrs;
+/* 0x0d4 */ u32 emc_ref;
+/* 0x0d8 */ u32 emc_pre;
+/* 0x0dc */ u32 emc_nop;
+/* 0x0e0 */ u32 emc_self_ref;
+/* 0x0e4 */ u32 emc_dpd;
+/* 0x0e8 */ u32 emc_mrw;
+/* 0x0ec */ u32 emc_mrr;
+/* 0x0f0 */ u32 emc_cmdq;
+/* 0x0f4 */ u32 emc_mc2emcq;
+/* 0x0f8 */ u32 emc_twtm_b01;
+/* 0x0fc */ u32 emc_tratm_b01;
+/* 0x100 */ u32 emc_fbio_spare;
+/* 0x104 */ u32 emc_fbio_cfg5;
+/* 0x108 */ u32 emc_twatm_b01;
+/* 0x10c */ u32 emc_tr2ref_b01;
+/* 0x110 */ u32 emc_pmacro_data_pi_ctrl_b01;
+/* 0x114 */ u32 emc_pmacro_cmd_pi_ctrl_b01;
+/* 0x118 */ u32 emc_pdex2cke;
+/* 0x11c */ u32 emc_cke2pden;
+/* 0x120 */ u32 emc_cfg_rsv;
+/* 0x124 */ u32 emc_acpd_control;
+/* 0x128 */ u32 emc_mpc;
+/* 0x12c */ u32 emc_emrs2;
+/* 0x130 */ u32 emc_emrs3;
+/* 0x134 */ u32 emc_mrw2;
+/* 0x138 */ u32 emc_mrw3;
+/* 0x13c */ u32 emc_mrw4;
+/* 0x140 */ u32 emc_clken_override;
+/* 0x144 */ u32 emc_r2r;
+/* 0x148 */ u32 emc_w2w;
+/* 0x14c */ u32 emc_einput;
+/* 0x150 */ u32 emc_einput_duration;
+/* 0x154 */ u32 emc_puterm_extra;
+/* 0x158 */ u32 emc_tckesr;
+/* 0x15c */ u32 emc_tpd;
+/* 0x160 */ u32 emc_stat_control;
+/* 0x164 */ u32 emc_stat_status;
+/* 0x168 */ u32 emc_rsvd_168[13];
+/* 0x19c */ u32 emc_stat_dram_clock_limit_lo;
+/* 0x1a0 */ u32 emc_stat_dram_clock_limit_hi;
+/* 0x1a4 */ u32 emc_stat_dram_clocks_lo;
+/* 0x1a8 */ u32 emc_stat_dram_clocks_hi;
+/* 0x1ac */ u32 emc_stat_dram_dev0_activate_cnt_lo;
+/* 0x1b0 */ u32 emc_stat_dram_dev0_activate_cnt_hi;
+/* 0x1b4 */ u32 emc_stat_dram_dev0_read_cnt_lo;
+/* 0x1b8 */ u32 emc_stat_dram_dev0_read_cnt_hi;
+/* 0x1bc */ u32 emc_stat_dram_dev0_read8_cnt_lo;
+/* 0x1c0 */ u32 emc_stat_dram_dev0_read8_cnt_hi;
+/* 0x1c4 */ u32 emc_stat_dram_dev0_write_cnt_lo;
+/* 0x1c8 */ u32 emc_stat_dram_dev0_write_cnt_hi;
+/* 0x1cc */ u32 emc_stat_dram_dev0_write8_cnt_lo;
+/* 0x1d0 */ u32 emc_stat_dram_dev0_write8_cnt_hi;
+/* 0x1d4 */ u32 emc_stat_dram_dev0_ref_cnt_lo;
+/* 0x1d8 */ u32 emc_stat_dram_dev0_ref_cnt_hi;
+/* 0x1dc */ u32 emc_stat_dram_dev0_extclks_cke_eq0_no_banks_active_clks_lo;
+/* 0x1e0 */ u32 emc_stat_dram_dev0_extclks_cke_eq0_no_banks_active_clks_hi;
+/* 0x1e4 */ u32 emc_stat_dram_dev0_clkstop_cke_eq0_no_banks_active_clks_lo;
+/* 0x1e8 */ u32 emc_stat_dram_dev0_clkstop_cke_eq0_no_banks_active_clks_hi;
+/* 0x1ec */ u32 emc_stat_dram_dev0_extclks_cke_eq1_no_banks_active_clks_lo;
+/* 0x1f0 */ u32 emc_stat_dram_dev0_extclks_cke_eq1_no_banks_active_clks_hi;
+/* 0x1f4 */ u32 emc_stat_dram_dev0_clkstop_cke_eq1_no_banks_active_clks_lo;
+/* 0x1f8 */ u32 emc_stat_dram_dev0_clkstop_cke_eq1_no_banks_active_clks_hi;
+/* 0x1fc */ u32 emc_stat_dram_dev0_extclks_cke_eq0_some_banks_active_clks_lo;
+/* 0x200 */ u32 emc_stat_dram_dev0_extclks_cke_eq0_some_banks_active_clks_hi;
+/* 0x204 */ u32 emc_stat_dram_dev0_clkstop_cke_eq0_some_banks_active_clks_lo;
+/* 0x208 */ u32 emc_stat_dram_dev0_clkstop_cke_eq0_some_banks_active_clks_hi;
+/* 0x20c */ u32 emc_stat_dram_dev0_extclks_cke_eq1_some_banks_active_clks_lo;
+/* 0x210 */ u32 emc_stat_dram_dev0_extclks_cke_eq1_some_banks_active_clks_hi;
+/* 0x214 */ u32 emc_stat_dram_dev0_clkstop_cke_eq1_some_banks_active_clks_lo;
+/* 0x218 */ u32 emc_stat_dram_dev0_clkstop_cke_eq1_some_banks_active_clks_hi;
+/* 0x21c */ u32 emc_stat_dram_dev0_sr_cke_eq0_clks_lo;
+/* 0x220 */ u32 emc_stat_dram_dev0_sr_cke_eq0_clks_hi;
+/* 0x224 */ u32 emc_stat_dram_dev0_dsr;
+/* 0x228 */ u32 emc_stat_dram_dev1_activate_cnt_lo;
+/* 0x22c */ u32 emc_stat_dram_dev1_activate_cnt_hi;
+/* 0x230 */ u32 emc_stat_dram_dev1_read_cnt_lo;
+/* 0x234 */ u32 emc_stat_dram_dev1_read_cnt_hi;
+/* 0x238 */ u32 emc_stat_dram_dev1_read8_cnt_lo;
+/* 0x23c */ u32 emc_stat_dram_dev1_read8_cnt_hi;
+/* 0x240 */ u32 emc_stat_dram_dev1_write_cnt_lo;
+/* 0x244 */ u32 emc_stat_dram_dev1_write_cnt_hi;
+/* 0x248 */ u32 emc_stat_dram_dev1_write8_cnt_lo;
+/* 0x24c */ u32 emc_stat_dram_dev1_write8_cnt_hi;
+/* 0x250 */ u32 emc_stat_dram_dev1_ref_cnt_lo;
+/* 0x254 */ u32 emc_stat_dram_dev1_ref_cnt_hi;
+/* 0x258 */ u32 emc_stat_dram_dev1_extclks_cke_eq0_no_banks_active_clks_lo;
+/* 0x25c */ u32 emc_stat_dram_dev1_extclks_cke_eq0_no_banks_active_clks_hi;
+/* 0x260 */ u32 emc_stat_dram_dev1_clkstop_cke_eq0_no_banks_active_clks_lo;
+/* 0x264 */ u32 emc_stat_dram_dev1_clkstop_cke_eq0_no_banks_active_clks_hi;
+/* 0x268 */ u32 emc_stat_dram_dev1_extclks_cke_eq1_no_banks_active_clks_lo;
+/* 0x26c */ u32 emc_stat_dram_dev1_extclks_cke_eq1_no_banks_active_clks_hi;
+/* 0x270 */ u32 emc_stat_dram_dev1_clkstop_cke_eq1_no_banks_active_clks_lo;
+/* 0x274 */ u32 emc_stat_dram_dev1_clkstop_cke_eq1_no_banks_active_clks_hi;
+/* 0x278 */ u32 emc_stat_dram_dev1_extclks_cke_eq0_some_banks_active_clks_lo;
+/* 0x27c */ u32 emc_stat_dram_dev1_extclks_cke_eq0_some_banks_active_clks_hi;
+/* 0x280 */ u32 emc_stat_dram_dev1_clkstop_cke_eq0_some_banks_active_clks_lo;
+/* 0x284 */ u32 emc_stat_dram_dev1_clkstop_cke_eq0_some_banks_active_clks_hi;
+/* 0x288 */ u32 emc_stat_dram_dev1_extclks_cke_eq1_some_banks_active_clks_lo;
+/* 0x28c */ u32 emc_stat_dram_dev1_extclks_cke_eq1_some_banks_active_clks_hi;
+/* 0x290 */ u32 emc_stat_dram_dev1_clkstop_cke_eq1_some_banks_active_clks_lo;
+/* 0x294 */ u32 emc_stat_dram_dev1_clkstop_cke_eq1_some_banks_active_clks_hi;
+/* 0x298 */ u32 emc_stat_dram_dev1_sr_cke_eq0_clks_lo;
+/* 0x29c */ u32 emc_stat_dram_dev1_sr_cke_eq0_clks_hi;
+/* 0x2a0 */ u32 emc_stat_dram_dev1_dsr;
+/* 0x2a4 */ u32 emc_auto_cal_config;
+/* 0x2a8 */ u32 emc_auto_cal_interval;
+/* 0x2ac */ u32 emc_auto_cal_status;
+/* 0x2b0 */ u32 emc_req_ctrl;
+/* 0x2b4 */ u32 emc_emc_status;
+/* 0x2b8 */ u32 emc_cfg_2;
+/* 0x2bc */ u32 emc_cfg_dig_dll;
+/* 0x2c0 */ u32 emc_cfg_dig_dll_period;
+/* 0x2c4 */ u32 emc_dig_dll_status;
+/* 0x2c8 */ u32 emc_cfg_dig_dll_1;
+/* 0x2cc */ u32 emc_rdv_mask;
+/* 0x2d0 */ u32 emc_wdv_mask;
+/* 0x2d4 */ u32 emc_rdv_early_mask;
+/* 0x2d8 */ u32 emc_rdv_early;
+/* 0x2dc */ u32 emc_auto_cal_config8;
+/* 0x2e0 */ u32 emc_zcal_interval;
+/* 0x2e4 */ u32 emc_zcal_wait_cnt;
+/* 0x2e8 */ u32 emc_zcal_mrw_cmd;
+/* 0x2ec */ u32 emc_zq_cal;
+/* 0x2f0 */ u32 emc_rsvd_2f0;
+/* 0x2f4 */ u32 emc_xm2comppadctrl3;
+/* 0x2f8 */ u32 emc_auto_cal_vref_sel_0;
+/* 0x2fc */ u32 emc_rsvd_2fc;
+/* 0x300 */ u32 emc_auto_cal_vref_sel_1;
+/* 0x304 */ u32 emc_pmacro_pmu_ctrl_b01;
+/* 0x308 */ u32 emc_pmacro_xm2comp_pmu_ctrl_b01;
+/* 0x30c */ u32 emc_xm2comppadctrl;
+/* 0x310 */ u32 emc_fdpd_ctrl_dq;
+/* 0x314 */ u32 emc_fdpd_ctrl_cmd;
+/* 0x318 */ u32 emc_pmacro_cmd_brick_ctrl_fdpd;
+/* 0x31c */ u32 emc_pmacro_data_brick_ctrl_fdpd;
+/* 0x320 */ u32 emc_rsvd_320;
+/* 0x324 */ u32 emc_scratch0;
+/* 0x328 */ u32 emc_rsvd_328[2];
+/* 0x330 */ u32 emc_pmacro_brick_ctrl_rfu1;
+/* 0x334 */ u32 emc_pmacro_brick_ctrl_rfu2;
+/* 0x338 */ u32 emc_rsvd_338[18];
+/* 0x380 */ u32 emc_cmd_mapping_cmd0_0;
+/* 0x384 */ u32 emc_cmd_mapping_cmd0_1;
+/* 0x388 */ u32 emc_cmd_mapping_cmd0_2;
+/* 0x38c */ u32 emc_cmd_mapping_cmd1_0;
+/* 0x390 */ u32 emc_cmd_mapping_cmd1_1;
+/* 0x394 */ u32 emc_cmd_mapping_cmd1_2;
+/* 0x398 */ u32 emc_cmd_mapping_cmd2_0;
+/* 0x39c */ u32 emc_cmd_mapping_cmd2_1;
+/* 0x3a0 */ u32 emc_cmd_mapping_cmd2_2;
+/* 0x3a4 */ u32 emc_cmd_mapping_cmd3_0;
+/* 0x3a8 */ u32 emc_cmd_mapping_cmd3_1;
+/* 0x3ac */ u32 emc_cmd_mapping_cmd3_2;
+/* 0x3b0 */ u32 emc_cmd_mapping_byte;
+/* 0x3b4 */ u32 emc_tr_timing_0;
+/* 0x3b8 */ u32 emc_tr_ctrl_0;
+/* 0x3bc */ u32 emc_tr_ctrl_1;
+/* 0x3c0 */ u32 emc_switch_back_ctrl;
+/* 0x3c4 */ u32 emc_tr_rdv;
+/* 0x3c8 */ u32 emc_stall_then_exe_before_clkchange;
+/* 0x3cc */ u32 emc_stall_then_exe_after_clkchange;
+/* 0x3d0 */ u32 emc_unstall_rw_after_clkchange;
+/* 0x3d4 */ u32 emc_auto_cal_status2;
+/* 0x3d8 */ u32 emc_sel_dpd_ctrl;
+/* 0x3dc */ u32 emc_pre_refresh_req_cnt;
+/* 0x3e0 */ u32 emc_dyn_self_ref_control;
+/* 0x3e4 */ u32 emc_txsrdll;
+/* 0x3e8 */ u32 emc_ccfifo_addr;
+/* 0x3ec */ u32 emc_ccfifo_data;
+/* 0x3f0 */ u32 emc_ccfifo_status;
+/* 0x3f4 */ u32 emc_tr_qpop;
+/* 0x3f8 */ u32 emc_tr_rdv_mask;
+/* 0x3fc */ u32 emc_tr_qsafe;
+/* 0x400 */ u32 emc_tr_qrst;
+/* 0x404 */ u32 emc_swizzle_rank0_byte0;
+/* 0x408 */ u32 emc_swizzle_rank0_byte1;
+/* 0x40c */ u32 emc_swizzle_rank0_byte2;
+/* 0x410 */ u32 emc_swizzle_rank0_byte3;
+/* 0x414 */ u32 emc_rsvd_414;
+/* 0x418 */ u32 emc_swizzle_rank1_byte0;
+/* 0x41c */ u32 emc_swizzle_rank1_byte1;
+/* 0x420 */ u32 emc_swizzle_rank1_byte2;
+/* 0x424 */ u32 emc_swizzle_rank1_byte3;
+/* 0x428 */ u32 emc_issue_qrst;
+/* 0x42c */ u32 emc_auto_cal_config9_b01;
+/* 0x430 */ u32 emc_rsvd_430[4];
+/* 0x440 */ u32 emc_pmc_scratch1;
+/* 0x444 */ u32 emc_pmc_scratch2;
+/* 0x448 */ u32 emc_pmc_scratch3;
+/* 0x44c */ u32 emc_pmacro_ddllcal_en_b01;
+/* 0x450 */ u32 emc_rsvd_450[2];
+/* 0x458 */ u32 emc_auto_cal_config2;
+/* 0x45c */ u32 emc_auto_cal_config3;
+/* 0x460 */ u32 emc_tr_dvfs;
+/* 0x464 */ u32 emc_auto_cal_channel;
+/* 0x468 */ u32 emc_ibdly;
+/* 0x46c */ u32 emc_obdly;
+/* 0x470 */ u32 emc_rsvd_470[4];
+/* 0x480 */ u32 emc_txdsrvttgen;
+/* 0x484 */ u32 emc_rsvd_484[2];
+/* 0x48c */ u32 emc_we_duration;
+/* 0x490 */ u32 emc_ws_duration;
+/* 0x494 */ u32 emc_wev;
+/* 0x498 */ u32 emc_wsv;
+/* 0x49c */ u32 emc_cfg_3;
+/* 0x4a0 */ u32 emc_mrw5;
+/* 0x4a4 */ u32 emc_mrw6;
+/* 0x4a8 */ u32 emc_mrw7;
+/* 0x4ac */ u32 emc_mrw8;
+/* 0x4b0 */ u32 emc_mrw9;
+/* 0x4b4 */ u32 emc_mrw10;
+/* 0x4b8 */ u32 emc_mrw11;
+/* 0x4bc */ u32 emc_mrw12;
+/* 0x4c0 */ u32 emc_mrw13;
+/* 0x4c4 */ u32 emc_mrw14;
+/* 0x4c8 */ u32 emc_rsvd_4c8[2];
+/* 0x4d0 */ u32 emc_mrw15;
+/* 0x4d4 */ u32 emc_cfg_sync;
+/* 0x4d8 */ u32 emc_fdpd_ctrl_cmd_no_ramp;
+/* 0x4dc */ u32 emc_rsvd_4dc;
+/* 0x4e0 */ u32 emc_wdv_chk;
+/* 0x4e4 */ u32 emc_rsvd_4e4[28];
+/* 0x554 */ u32 emc_cfg_pipe_2;
+/* 0x558 */ u32 emc_cfg_pipe_clk;
+/* 0x55c */ u32 emc_cfg_pipe_1;
+/* 0x560 */ u32 emc_cfg_pipe;
+/* 0x564 */ u32 emc_qpop;
+/* 0x568 */ u32 emc_quse_width;
+/* 0x56c */ u32 emc_puterm_width;
+/* 0x570 */ u32 emc_rsvd_570;
+/* 0x574 */ u32 emc_auto_cal_config7;
+/* 0x578 */ u32 emc_xm2comppadctrl2;
+/* 0x57c */ u32 emc_comp_pad_sw_ctrl;
+/* 0x580 */ u32 emc_refctrl2;
+/* 0x584 */ u32 emc_fbio_cfg7;
+/* 0x588 */ u32 emc_data_brlshft_0;
+/* 0x58c */ u32 emc_data_brlshft_1;
+/* 0x590 */ u32 emc_rfcpb;
+/* 0x594 */ u32 emc_dqs_brlshft_0;
+/* 0x598 */ u32 emc_dqs_brlshft_1;
+/* 0x59c */ u32 emc_cmd_brlshft_0;
+/* 0x5a0 */ u32 emc_cmd_brlshft_1;
+/* 0x5a4 */ u32 emc_cmd_brlshft_2;
+/* 0x5a8 */ u32 emc_cmd_brlshft_3;
+/* 0x5ac */ u32 emc_quse_brlshft_0;
+/* 0x5b0 */ u32 emc_auto_cal_config4;
+/* 0x5b4 */ u32 emc_auto_cal_config5;
+/* 0x5b8 */ u32 emc_quse_brlshft_1;
+/* 0x5bc */ u32 emc_quse_brlshft_2;
+/* 0x5c0 */ u32 emc_ccdmw;
+/* 0x5c4 */ u32 emc_quse_brlshft_3;
+/* 0x5c8 */ u32 emc_fbio_cfg8;
+/* 0x5cc */ u32 emc_auto_cal_config6;
+/* 0x5d0 */ u32 emc_protobist_config_adr_1;
+/* 0x5d4 */ u32 emc_protobist_config_adr_2;
+/* 0x5d8 */ u32 emc_protobist_misc;
+/* 0x5dc */ u32 emc_protobist_wdata_lower;
+/* 0x5e0 */ u32 emc_protobist_wdata_upper;
+ union {
+/* 0x5e4 */ u32 emc_dll_cfg_0;
+/* 0x5e4 */ u32 emc_pmacro_dll_cfg_0_b01;
+ };
+ union {
+/* 0x5e8 */ u32 emc_dll_cfg_1;
+/* 0x5e8 */ u32 emc_pmacro_dll_cfg_1_b01;
+ };
+/* 0x5ec */ u32 emc_protobist_rdata;
+/* 0x5f0 */ u32 emc_config_sample_delay;
+/* 0x5f4 */ u32 emc_cfg_update;
+/* 0x5f8 */ u32 emc_pmacro_dll_cfg_2_b01;
+/* 0x5fc */ u32 emc_rsvd_5fc;
+/* 0x600 */ u32 emc_pmacro_quse_ddll_rank0_0;
+/* 0x604 */ u32 emc_pmacro_quse_ddll_rank0_1;
+/* 0x608 */ u32 emc_pmacro_quse_ddll_rank0_2;
+/* 0x60c */ u32 emc_pmacro_quse_ddll_rank0_3;
+/* 0x610 */ u32 emc_pmacro_quse_ddll_rank0_4;
+/* 0x614 */ u32 emc_pmacro_quse_ddll_rank0_5;
+/* 0x618 */ u32 emc_rsvd_618[2];
+/* 0x620 */ u32 emc_pmacro_quse_ddll_rank1_0;
+/* 0x624 */ u32 emc_pmacro_quse_ddll_rank1_1;
+/* 0x628 */ u32 emc_pmacro_quse_ddll_rank1_2;
+/* 0x62c */ u32 emc_pmacro_quse_ddll_rank1_3;
+/* 0x630 */ u32 emc_pmacro_quse_ddll_rank1_4;
+/* 0x634 */ u32 emc_pmacro_quse_ddll_rank1_5;
+/* 0x638 */ u32 emc_rsvd_638[2];
+/* 0x640 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
+/* 0x644 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
+/* 0x648 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
+/* 0x64c */ u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
+/* 0x650 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
+/* 0x654 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
+/* 0x658 */ u32 emc_rsvd_658[2];
+/* 0x660 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
+/* 0x664 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
+/* 0x668 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
+/* 0x66c */ u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
+/* 0x670 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
+/* 0x674 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
+/* 0x678 */ u32 emc_rsvd_678[2];
+/* 0x680 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
+/* 0x684 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
+/* 0x688 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
+/* 0x68c */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
+/* 0x690 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
+/* 0x694 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
+/* 0x698 */ u32 emc_rsvd_698[2];
+/* 0x6a0 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
+/* 0x6a4 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
+/* 0x6a8 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
+/* 0x6ac */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
+/* 0x6b0 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
+/* 0x6b4 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
+/* 0x6b8 */ u32 emc_rsvd_6b8[2];
+/* 0x6c0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
+/* 0x6c4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
+/* 0x6c8 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
+/* 0x6cc */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
+/* 0x6d0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_4;
+/* 0x6d4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_5;
+/* 0x6d8 */ u32 emc_rsvd_6d8[2];
+/* 0x6e0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
+/* 0x6e4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
+/* 0x6e8 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
+/* 0x6ec */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
+/* 0x6f0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_4;
+/* 0x6f4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_5;
+/* 0x6f8 */ u32 emc_rsvd_6f8[2];
+/* 0x700 */ u32 emc_pmacro_autocal_cfg_0;
+/* 0x704 */ u32 emc_pmacro_autocal_cfg_1;
+/* 0x708 */ u32 emc_pmacro_autocal_cfg_2;
+/* 0x70c */ u32 emc_rsvd_70c[5];
+/* 0x720 */ u32 emc_pmacro_tx_pwrd_0;
+/* 0x724 */ u32 emc_pmacro_tx_pwrd_1;
+/* 0x728 */ u32 emc_pmacro_tx_pwrd_2;
+/* 0x72c */ u32 emc_pmacro_tx_pwrd_3;
+/* 0x730 */ u32 emc_pmacro_tx_pwrd_4;
+/* 0x734 */ u32 emc_pmacro_tx_pwrd_5;
+/* 0x738 */ u32 emc_rsvd_738[2];
+/* 0x740 */ u32 emc_pmacro_tx_sel_clk_src_0;
+/* 0x744 */ u32 emc_pmacro_tx_sel_clk_src_1;
+/* 0x748 */ u32 emc_pmacro_tx_sel_clk_src_2;
+/* 0x74c */ u32 emc_pmacro_tx_sel_clk_src_3;
+/* 0x750 */ u32 emc_pmacro_tx_sel_clk_src_4;
+/* 0x754 */ u32 emc_pmacro_tx_sel_clk_src_5;
+/* 0x758 */ u32 emc_rsvd_758[2];
+/* 0x760 */ u32 emc_pmacro_ddll_bypass;
+/* 0x764 */ u32 emc_rsvd_764[3];
+/* 0x770 */ u32 emc_pmacro_ddll_pwrd_0;
+/* 0x774 */ u32 emc_pmacro_ddll_pwrd_1;
+/* 0x778 */ u32 emc_pmacro_ddll_pwrd_2;
+/* 0x77c */ u32 emc_rsvd_77c;
+/* 0x780 */ u32 emc_pmacro_cmd_ctrl_0;
+/* 0x784 */ u32 emc_pmacro_cmd_ctrl_1;
+/* 0x788 */ u32 emc_pmacro_cmd_ctrl_2;
+/* 0x78c */ u32 emc_rsvd_78c[29];
+/* 0x800 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
+/* 0x804 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
+/* 0x808 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
+/* 0x80c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
+/* 0x810 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
+/* 0x814 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
+/* 0x818 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
+/* 0x81c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
+/* 0x820 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
+/* 0x824 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
+/* 0x828 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
+/* 0x82c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
+/* 0x830 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
+/* 0x834 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
+/* 0x838 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
+/* 0x83c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
+/* 0x840 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
+/* 0x844 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
+/* 0x848 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
+/* 0x84c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
+/* 0x850 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
+/* 0x854 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
+/* 0x858 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
+/* 0x85c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
+/* 0x860 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
+/* 0x864 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
+/* 0x868 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
+/* 0x86c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
+/* 0x870 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
+/* 0x874 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
+/* 0x878 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
+/* 0x87c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
+/* 0x880 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
+/* 0x884 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
+/* 0x888 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
+/* 0x88c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
+/* 0x890 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
+/* 0x894 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
+/* 0x898 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
+/* 0x89c */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
+/* 0x8a0 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
+/* 0x8a4 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
+/* 0x8a8 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
+/* 0x8ac */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
+/* 0x8b0 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
+/* 0x8b4 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
+/* 0x8b8 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
+/* 0x8bc */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
+/* 0x8c0 */ u32 emc_rsvd_8c0[16];
+/* 0x900 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
+/* 0x904 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
+/* 0x908 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
+/* 0x90c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
+/* 0x910 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
+/* 0x914 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
+/* 0x918 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
+/* 0x91c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
+/* 0x920 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
+/* 0x924 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
+/* 0x928 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
+/* 0x92c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
+/* 0x930 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
+/* 0x934 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
+/* 0x938 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
+/* 0x93c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
+/* 0x940 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
+/* 0x944 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
+/* 0x948 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
+/* 0x94c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
+/* 0x950 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
+/* 0x954 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
+/* 0x958 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
+/* 0x95c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
+/* 0x960 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
+/* 0x964 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
+/* 0x968 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
+/* 0x96c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
+/* 0x970 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
+/* 0x974 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
+/* 0x978 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
+/* 0x97c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
+/* 0x980 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
+/* 0x984 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
+/* 0x988 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
+/* 0x98c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
+/* 0x990 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
+/* 0x994 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
+/* 0x998 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
+/* 0x99c */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
+/* 0x9a0 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
+/* 0x9a4 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
+/* 0x9a8 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
+/* 0x9ac */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
+/* 0x9b0 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
+/* 0x9b4 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
+/* 0x9b8 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
+/* 0x9bc */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
+/* 0x9c0 */ u32 emc_rsvd_9c0[16];
+/* 0xa00 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
+/* 0xa04 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
+/* 0xa08 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
+/* 0xa0c */ u32 emc_rsvd_a0c;
+/* 0xa10 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
+/* 0xa14 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
+/* 0xa18 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
+/* 0xa1c */ u32 emc_rsvd_a1c;
+/* 0xa20 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
+/* 0xa24 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
+/* 0xa28 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
+/* 0xa2c */ u32 emc_rsvd_a2c;
+/* 0xa30 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
+/* 0xa34 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
+/* 0xa38 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
+/* 0xa3c */ u32 emc_rsvd_a3c;
+/* 0xa40 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
+/* 0xa44 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
+/* 0xa48 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
+/* 0xa4c */ u32 emc_rsvd_a4c;
+/* 0xa50 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
+/* 0xa54 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
+/* 0xa58 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
+/* 0xa5c */ u32 emc_rsvd_a5c;
+/* 0xa60 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
+/* 0xa64 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
+/* 0xa68 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
+/* 0xa6c */ u32 emc_rsvd_a6c;
+/* 0xa70 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
+/* 0xa74 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
+/* 0xa78 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
+/* 0xa7c */ u32 emc_rsvd_a7c;
+/* 0xa80 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_0;
+/* 0xa84 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_1;
+/* 0xa88 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_2;
+/* 0xa8c */ u32 emc_rsvd_a8c;
+/* 0xa90 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_0;
+/* 0xa94 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_1;
+/* 0xa98 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_2;
+/* 0xa9c */ u32 emc_rsvd_a9c;
+/* 0xaa0 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_0;
+/* 0xaa4 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_1;
+/* 0xaa8 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_2;
+/* 0xaac */ u32 emc_rsvd_aac;
+/* 0xab0 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_0;
+/* 0xab4 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_1;
+/* 0xab8 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_2;
+/* 0xabc */ u32 emc_rsvd_abc[17];
+/* 0xb00 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
+/* 0xb04 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
+/* 0xb08 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
+/* 0xb0c */ u32 emc_rsvd_b0c;
+/* 0xb10 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
+/* 0xb14 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
+/* 0xb18 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
+/* 0xb1c */ u32 emc_rsvd_b1c;
+/* 0xb20 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
+/* 0xb24 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
+/* 0xb28 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
+/* 0xb2c */ u32 emc_rsvd_b2c;
+/* 0xb30 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
+/* 0xb34 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
+/* 0xb38 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
+/* 0xb3c */ u32 emc_rsvd_b3c;
+/* 0xb40 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
+/* 0xb44 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
+/* 0xb48 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
+/* 0xb4c */ u32 emc_rsvd_b4c;
+/* 0xb50 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
+/* 0xb54 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
+/* 0xb58 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
+/* 0xb5c */ u32 emc_rsvd_b5c;
+/* 0xb60 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
+/* 0xb64 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
+/* 0xb68 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
+/* 0xb6c */ u32 emc_rsvd_b6c;
+/* 0xb70 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
+/* 0xb74 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
+/* 0xb78 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
+/* 0xb7c */ u32 emc_rsvd_b7c;
+/* 0xb80 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_0;
+/* 0xb84 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_1;
+/* 0xb88 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_2;
+/* 0xb8c */ u32 emc_rsvd_b8c;
+/* 0xb90 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_0;
+/* 0xb94 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_1;
+/* 0xb98 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_2;
+/* 0xb9c */ u32 emc_rsvd_b9c;
+/* 0xba0 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_0;
+/* 0xba4 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_1;
+/* 0xba8 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_2;
+/* 0xbac */ u32 emc_rsvd_bac;
+/* 0xbb0 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_0;
+/* 0xbb4 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_1;
+/* 0xbb8 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_2;
+/* 0xbbc */ u32 emc_rsvd_bbc[9];
+/* 0xbe0 */ u32 emc_pmacro_ib_vref_dq_0;
+/* 0xbe4 */ u32 emc_pmacro_ib_vref_dq_1;
+/* 0xbe8 */ u32 emc_pmacro_ib_vref_dq_2;
+/* 0xbec */ u32 emc_rsvd_bec;
+/* 0xbf0 */ u32 emc_pmacro_ib_vref_dqs_0;
+/* 0xbf4 */ u32 emc_pmacro_ib_vref_dqs_1;
+/* 0xbf8 */ u32 emc_pmacro_ib_vref_dqs_2;
+/* 0xbfc */ u32 emc_rsvd_bfc;
+/* 0xc00 */ u32 emc_pmacro_ddll_long_cmd_0;
+/* 0xc04 */ u32 emc_pmacro_ddll_long_cmd_1;
+/* 0xc08 */ u32 emc_pmacro_ddll_long_cmd_2;
+/* 0xc0c */ u32 emc_pmacro_ddll_long_cmd_3;
+/* 0xc10 */ u32 emc_pmacro_ddll_long_cmd_4;
+/* 0xc14 */ u32 emc_pmacro_ddll_long_cmd_5;
+/* 0xc18 */ u32 emc_rsvd_c18[2];
+/* 0xc20 */ u32 emc_pmacro_ddll_short_cmd_0;
+/* 0xc24 */ u32 emc_pmacro_ddll_short_cmd_1;
+/* 0xc28 */ u32 emc_pmacro_ddll_short_cmd_2;
+/* 0xc2c */ u32 emc_rsvd_c2c;
+/* 0xc30 */ u32 emc_pmacro_cfg_pm_global_0;
+/* 0xc34 */ u32 emc_pmacro_vttgen_ctrl_0;
+/* 0xc38 */ u32 emc_pmacro_vttgen_ctrl_1;
+/* 0xc3c */ u32 emc_pmacro_bg_bias_ctrl_0;
+/* 0xc40 */ u32 emc_pmacro_pad_cfg_ctrl;
+/* 0xc44 */ u32 emc_pmacro_zctrl;
+/* 0xc48 */ u32 emc_pmacro_rx_term;
+/* 0xc4c */ u32 emc_pmacro_cmd_tx_drv;
+/* 0xc50 */ u32 emc_pmacro_cmd_pad_rx_ctrl;
+/* 0xc54 */ u32 emc_pmacro_data_pad_rx_ctrl;
+/* 0xc58 */ u32 emc_pmacro_cmd_rx_term_mode;
+/* 0xc5c */ u32 emc_pmacro_data_rx_term_mode;
+/* 0xc60 */ u32 emc_pmacro_cmd_pad_tx_ctrl;
+/* 0xc64 */ u32 emc_pmacro_data_pad_tx_ctrl;
+/* 0xc68 */ u32 emc_pmacro_common_pad_tx_ctrl_t210;
+/* 0xc6c */ u32 emc_pmacro_dsr_vttgen_ctrl_0_b01;
+/* 0xc70 */ u32 emc_pmacro_dq_tx_drv;
+/* 0xc74 */ u32 emc_pmacro_ca_tx_drv;
+/* 0xc78 */ u32 emc_pmacro_autocal_cfg_common;
+/* 0xc7c */ u32 emc_rsvd_c7c;
+/* 0xc80 */ u32 emc_pmacro_brick_mapping_0;
+/* 0xc84 */ u32 emc_pmacro_brick_mapping_1;
+/* 0xc88 */ u32 emc_pmacro_brick_mapping_2;
+/* 0xc8c */ u32 emc_stat_dram_io_extclks_cke_eq0_no_banks_active_clks_lo;
+/* 0xc90 */ u32 emc_stat_dram_io_extclks_cke_eq0_no_banks_active_clks_hi;
+/* 0xc94 */ u32 emc_stat_dram_io_clkstop_cke_eq0_no_banks_active_clks_lo;
+/* 0xc98 */ u32 emc_stat_dram_io_clkstop_cke_eq0_no_banks_active_clks_hi;
+/* 0xc9c */ u32 emc_stat_dram_io_extclks_cke_eq1_no_banks_active_clks_lo;
+/* 0xca0 */ u32 emc_stat_dram_io_extclks_cke_eq1_no_banks_active_clks_hi;
+/* 0xca4 */ u32 emc_stat_dram_io_clkstop_cke_eq1_no_banks_active_clks_lo;
+/* 0xca8 */ u32 emc_stat_dram_io_clkstop_cke_eq1_no_banks_active_clks_hi;
+/* 0xcac */ u32 emc_stat_dram_io_extclks_cke_eq0_some_banks_active_clks_lo;
+/* 0xcb0 */ u32 emc_stat_dram_io_extclks_cke_eq0_some_banks_active_clks_hi;
+/* 0xcb4 */ u32 emc_stat_dram_io_clkstop_cke_eq0_some_banks_active_clks_lo;
+/* 0xcb8 */ u32 emc_stat_dram_io_clkstop_cke_eq0_some_banks_active_clks_hi;
+/* 0xcbc */ u32 emc_stat_dram_io_extclks_cke_eq1_some_banks_active_clks_lo;
+/* 0xcc0 */ u32 emc_stat_dram_io_extclks_cke_eq1_some_banks_active_clks_hi;
+/* 0xcc4 */ u32 emc_stat_dram_io_clkstop_cke_eq1_some_banks_active_clks_lo;
+/* 0xcc8 */ u32 emc_stat_dram_io_clkstop_cke_eq1_some_banks_active_clks_hi;
+/* 0xccc */ u32 emc_stat_dram_io_sr_cke_eq0_clks_lo;
+/* 0xcd0 */ u32 emc_stat_dram_io_sr_cke_eq0_clks_hi;
+/* 0xcd4 */ u32 emc_stat_dram_io_dsr;
+/* 0xcd8 */ u32 emc_rsvd_cd8[2];
+/* 0xce0 */ u32 emc_pmacro_ddllcal_cal_t210;
+/* 0xce4 */ u32 emc_pmacro_ddll_offset;
+/* 0xce8 */ u32 emc_pmacro_ddll_periodic_offset;
+/* 0xcec */ u32 emc_rsvd_cec;
+/* 0xcf0 */ u32 emc_pmacro_vttgen_ctrl_2;
+/* 0xcf4 */ u32 emc_pmacro_ib_rxrt;
+/* 0xcf8 */ u32 emc_pmacro_training_ctrl_0;
+/* 0xcfc */ u32 emc_pmacro_training_ctrl_1;
+/* 0xd00 */ u32 emc_pmacro_ddllcal_cal_0_b01;
+/* 0xd04 */ u32 emc_pmacro_ddllcal_cal_1_b01;
+/* 0xd08 */ u32 emc_pmacro_ddllcal_cal_2_b01;
+/* 0xd0c */ u32 emc_pmacro_ddllcal_cal_3_b01;
+/* 0xd10 */ u32 emc_pmacro_ddllcal_cal_4_b01;
+/* 0xd14 */ u32 emc_pmacro_ddllcal_cal_5_b01;
+/* 0xd18 */ u32 emc_rsvd_d18[2];
+/* 0xd20 */ u32 emc_pmacro_dig_dll_status_0_b01;
+/* 0xd24 */ u32 emc_pmacro_dig_dll_status_1_b01;
+/* 0xd28 */ u32 emc_pmacro_dig_dll_status_2_b01;
+/* 0xd2c */ u32 emc_pmacro_dig_dll_status_3_b01;
+/* 0xd30 */ u32 emc_pmacro_dig_dll_status_4_b01;
+/* 0xd34 */ u32 emc_pmacro_dig_dll_status_5_b01;
+/* 0xd38 */ u32 emc_rsvd_d38[2];
+/* 0xd40 */ u32 emc_pmacro_perbit_fgcg_ctrl_0_b01;
+/* 0xd44 */ u32 emc_pmacro_perbit_fgcg_ctrl_1_b01;
+/* 0xd48 */ u32 emc_pmacro_perbit_fgcg_ctrl_2_b01;
+/* 0xd4c */ u32 emc_pmacro_perbit_fgcg_ctrl_3_b01;
+/* 0xd50 */ u32 emc_pmacro_perbit_fgcg_ctrl_4_b01;
+/* 0xd54 */ u32 emc_pmacro_perbit_fgcg_ctrl_5_b01;
+/* 0xd58 */ u32 emc_rsvd_d58[2];
+/* 0xd60 */ u32 emc_pmacro_perbit_rfu_ctrl_0_b01;
+/* 0xd64 */ u32 emc_pmacro_perbit_rfu_ctrl_1_b01;
+/* 0xd68 */ u32 emc_pmacro_perbit_rfu_ctrl_2_b01;
+/* 0xd6c */ u32 emc_pmacro_perbit_rfu_ctrl_3_b01;
+/* 0xd70 */ u32 emc_pmacro_perbit_rfu_ctrl_4_b01;
+/* 0xd74 */ u32 emc_pmacro_perbit_rfu_ctrl_5_b01;
+/* 0xd78 */ u32 emc_rsvd_d78[2];
+/* 0xd80 */ u32 emc_pmacro_perbit_rfu1_ctrl_0_b01;
+/* 0xd84 */ u32 emc_pmacro_perbit_rfu1_ctrl_1_b01;
+/* 0xd88 */ u32 emc_pmacro_perbit_rfu1_ctrl_2_b01;
+/* 0xd8c */ u32 emc_pmacro_perbit_rfu1_ctrl_3_b01;
+/* 0xd90 */ u32 emc_pmacro_perbit_rfu1_ctrl_4_b01;
+/* 0xd94 */ u32 emc_pmacro_perbit_rfu1_ctrl_5_b01;
+/* 0xd98 */ u32 emc_rsvd_d98[2];
+/* 0xda0 */ u32 emc_pmacro_pmu_out_eoff1_0_b01;
+/* 0xda4 */ u32 emc_pmacro_pmu_out_eoff1_1_b01;
+/* 0xda8 */ u32 emc_pmacro_pmu_out_eoff1_2_b01;
+/* 0xdac */ u32 emc_pmacro_pmu_out_eoff1_3_b01;
+/* 0xdb0 */ u32 emc_pmacro_pmu_out_eoff1_4_b01;
+/* 0xdb4 */ u32 emc_pmacro_pmu_out_eoff1_5_b01;
+/* 0xdb8 */ u32 emc_rsvd_db8[2];
+/* 0xdc0 */ u32 emc_pmacro_comp_pmu_out_b01;
+/* 0xdc4 */ u32 emc_rsvd_dc4[15];
+/* 0xe00 */ u32 emc_training_cmd;
+/* 0xe04 */ u32 emc_training_ctrl;
+/* 0xe08 */ u32 emc_training_status;
+/* 0xe0c */ u32 emc_training_quse_cors_ctrl;
+/* 0xe10 */ u32 emc_training_quse_fine_ctrl;
+/* 0xe14 */ u32 emc_training_quse_ctrl_misc;
+/* 0xe18 */ u32 emc_training_write_fine_ctrl;
+/* 0xe1c */ u32 emc_training_write_ctrl_misc;
+/* 0xe20 */ u32 emc_training_write_vref_ctrl;
+/* 0xe24 */ u32 emc_training_read_fine_ctrl;
+/* 0xe28 */ u32 emc_training_read_ctrl_misc;
+/* 0xe2c */ u32 emc_training_read_vref_ctrl;
+/* 0xe30 */ u32 emc_training_ca_fine_ctrl;
+/* 0xe34 */ u32 emc_training_ca_ctrl_misc;
+/* 0xe38 */ u32 emc_training_ca_ctrl_misc1;
+/* 0xe3c */ u32 emc_training_ca_vref_ctrl;
+/* 0xe40 */ u32 emc_training_ca_tadr_ctrl;
+/* 0xe44 */ u32 emc_training_settle;
+/* 0xe48 */ u32 emc_training_debug_ctrl;
+/* 0xe4c */ u32 emc_training_debug_dq0;
+/* 0xe50 */ u32 emc_training_debug_dq1;
+/* 0xe54 */ u32 emc_training_debug_dq2;
+/* 0xe58 */ u32 emc_training_debug_dq3;
+/* 0xe5c */ u32 emc_training_mpc;
+/* 0xe60 */ u32 emc_training_patram_ctrl;
+/* 0xe64 */ u32 emc_training_patram_dq;
+/* 0xe68 */ u32 emc_training_patram_dmi;
+/* 0xe6c */ u32 emc_training_vref_settle;
+/* 0xe70 */ u32 emc_training_rw_eye_center_ib_byte0;
+/* 0xe74 */ u32 emc_training_rw_eye_center_ib_byte1;
+/* 0xe78 */ u32 emc_training_rw_eye_center_ib_byte2;
+/* 0xe7c */ u32 emc_training_rw_eye_center_ib_byte3;
+/* 0xe80 */ u32 emc_training_rw_eye_center_ib_misc;
+/* 0xe84 */ u32 emc_training_rw_eye_center_ob_byte0;
+/* 0xe88 */ u32 emc_training_rw_eye_center_ob_byte1;
+/* 0xe8c */ u32 emc_training_rw_eye_center_ob_byte2;
+/* 0xe90 */ u32 emc_training_rw_eye_center_ob_byte3;
+/* 0xe94 */ u32 emc_training_rw_eye_center_ob_misc;
+/* 0xe98 */ u32 emc_training_rw_offset_ib_byte0;
+/* 0xe9c */ u32 emc_training_rw_offset_ib_byte1;
+/* 0xea0 */ u32 emc_training_rw_offset_ib_byte2;
+/* 0xea4 */ u32 emc_training_rw_offset_ib_byte3;
+/* 0xea8 */ u32 emc_training_rw_offset_ib_misc;
+/* 0xeac */ u32 emc_training_rw_offset_ob_byte0;
+/* 0xeb0 */ u32 emc_training_rw_offset_ob_byte1;
+/* 0xeb4 */ u32 emc_training_rw_offset_ob_byte2;
+/* 0xeb8 */ u32 emc_training_rw_offset_ob_byte3;
+/* 0xebc */ u32 emc_training_rw_offset_ob_misc;
+/* 0xec0 */ u32 emc_training_opt_ca_vref;
+/* 0xec4 */ u32 emc_training_opt_dq_ob_vref;
+/* 0xec8 */ u32 emc_training_opt_dq_ib_vref_rank0;
+/* 0xecc */ u32 emc_training_opt_dq_ib_vref_rank1;
+/* 0xed0 */ u32 emc_training_quse_vref_ctrl;
+/* 0xed4 */ u32 emc_training_opt_dqs_ib_vref_rank0;
+/* 0xed8 */ u32 emc_training_opt_dqs_ib_vref_rank1;
+/* 0xedc */ u32 emc_training_dramc_timing;
+} emc_regs_t210_t;
+
+#endif
diff --git a/bdk/mem/mc_t210.h b/bdk/mem/mc_t210.h
index ff96b9d8..26ed92f3 100644
--- a/bdk/mem/mc_t210.h
+++ b/bdk/mem/mc_t210.h
@@ -1,487 +1,549 @@
/*
- * Copyright (c) 2014, NVIDIA Corporation.
- * Copyright (c) 2018-2023, CTCaer
+ * Copyright (c) 2018-2025 CTCaer
*
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
*/
#ifndef _MC_T210_H_
#define _MC_T210_H_
-/*! MC SMMU registers */
-#define MC_SMMU_CONFIG 0x10
-#define MC_SMMU_TLB_CONFIG 0x14
-#define MC_SMMU_PTC_CONFIG 0x18
-#define MC_SMMU_PTB_ASID 0x1c
-#define MC_SMMU_PTB_DATA 0x20
-#define MC_SMMU_TLB_FLUSH 0x30
-#define MC_SMMU_PTC_FLUSH 0x34
-#define MC_SMMU_ASID_SECURITY 0x38
-#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
+/* Memory Controller registers */
+#define MC_INTSTATUS 0x0
+#define MC_INTMASK 0x4
+#define MC_ERR_STATUS 0x8
+#define MC_ERR_ADR 0xC
+#define MC_SMMU_CONFIG 0x10
+#define MC_SMMU_TLB_CONFIG 0x14
+#define MC_SMMU_PTC_CONFIG 0x18
+#define MC_SMMU_PTB_ASID 0x1C
+#define MC_SMMU_PTB_DATA 0x20
+#define MC_SMMU_TLB_FLUSH 0x30
+#define MC_SMMU_PTC_FLUSH 0x34
+#define MC_SMMU_ASID_SECURITY 0x38
+#define MC_SMMU_ASID_SECURITY_1 0x3C
+#define MC_SMMU_CLIENT_CONFIG0 0x40
+#define MC_SMMU_CLIENT_CONFIG1 0x44
+#define MC_SMMU_CLIENT_CONFIG2 0x48
+#define MC_SMMU_CLIENT_CONFIG3 0x4C
+#define MC_EMEM_CFG 0x50
+#define MC_EMEM_ADR_CFG 0x54
+#define MC_EMEM_ADR_CFG_DEV0 0x58
+#define MC_EMEM_ADR_CFG_DEV1 0x5C
+#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
+#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
+#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
+#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6C
+#define MC_SECURITY_CFG0 0x70
+#define MC_SECURITY_CFG1 0x74
+#define MC_SECURITY_RSV 0x7C
+#define MC_EMEM_ARB_CFG 0x90
+#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
+#define MC_EMEM_ARB_TIMING_RCD 0x98
+#define MC_EMEM_ARB_TIMING_RP 0x9C
+#define MC_EMEM_ARB_TIMING_RC 0xA0
+#define MC_EMEM_ARB_TIMING_RAS 0xA4
+#define MC_EMEM_ARB_TIMING_FAW 0xA8
+#define MC_EMEM_ARB_TIMING_RRD 0xAC
+#define MC_EMEM_ARB_TIMING_RAP2PRE 0xB0
+#define MC_EMEM_ARB_TIMING_WAP2PRE 0xB4
+#define MC_EMEM_ARB_TIMING_R2R 0xB8
+#define MC_EMEM_ARB_TIMING_W2W 0xBC
+#define MC_EMEM_ARB_TIMING_R2W 0xC0
+#define MC_EMEM_ARB_TIMING_W2R 0xC4
+#define MC_EMEM_ARB_MISC2 0xC8
+#define MC_EMEM_ARB_DA_TURNS 0xD0
+#define MC_EMEM_ARB_DA_COVERS 0xD4
+#define MC_EMEM_ARB_MISC0 0xD8
+#define MC_EMEM_ARB_MISC1 0xDC
+#define MC_EMEM_ARB_RING1_THROTTLE 0xE0
+#define MC_EMEM_ARB_RING3_THROTTLE 0xE4
+#define MC_EMEM_ARB_OVERRIDE 0xE8
+#define MC_EMEM_ARB_RSV 0xEC
+#define MC_CLKEN_OVERRIDE 0xF4
+#define MC_TIMING_CONTROL_DBG 0xF8
+#define MC_TIMING_CONTROL 0xFC
+#define MC_STAT_CONTROL 0x100
+#define MC_STAT_STATUS 0x104
+#define MC_STAT_EMC_CLOCK_LIMIT 0x108
+#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10C
+#define MC_STAT_EMC_CLOCKS 0x110
+#define MC_STAT_EMC_CLOCKS_MSBS 0x114
+#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
+#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11C
+#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
+#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
+#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12C
+#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
+#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
+#define MC_STAT_EMC_SET0_COUNT 0x138
+#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13C
+#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
+#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
+#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
+#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14C
+#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
+#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
+#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15C
+#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
+#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
+#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16C
+#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
+#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
+#define MC_STAT_EMC_SET1_COUNT 0x178
+#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17C
+#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
+#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
+#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
+#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18C
+#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
+#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
+#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19C
+#define MC_STAT_EMC_FILTER_SET0_ASID 0x1A0
+#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1A8
+#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1AC
+#define MC_STAT_EMC_FILTER_SET1_ASID 0x1B0
+#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1B8
+#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1BC
+#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1C0
+#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1C8
+#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1CC
+#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1D0
+#define MC_SMMU_STATS_TLB_HIT_MISS_SOURCE 0x1EC
+#define MC_SMMU_STATS_TLB_HIT_COUNT 0x1F0
+#define MC_SMMU_STATS_TLB_MISS_COUNT 0x1F4
+#define MC_SMMU_STATS_PTC_HIT_COUNT 0x1F8
+#define MC_SMMU_STATS_PTC_MISS_COUNT 0x1FC
+#define MC_CLIENT_HOTRESET_CTRL 0x200
+#define MC_CLIENT_HOTRESET_STATUS 0x204
+#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
+#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20C
+#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
+#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
+#define MC_EMEM_ARB_HYSTERESIS_0 0x218
+#define MC_EMEM_ARB_HYSTERESIS_1 0x21C
+#define MC_EMEM_ARB_HYSTERESIS_2 0x220
+#define MC_EMEM_ARB_HYSTERESIS_3 0x224
+#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
+#define MC_SMMU_TRANSLATION_ENABLE_1 0x22C
+#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
+#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
+#define MC_SMMU_AFI_ASID 0x238
+#define MC_SMMU_AVPC_ASID 0x23C
+#define MC_SMMU_DC_ASID 0x240
+#define MC_SMMU_DCB_ASID 0x244
+#define MC_SMMU_HC_ASID 0x250
+#define MC_SMMU_HDA_ASID 0x254
+#define MC_SMMU_ISP2_ASID 0x258
+#define MC_SMMU_NVENC_ASID 0x264
+#define MC_SMMU_PPCS_ASID 0x270
+#define MC_SMMU_SATA_ASID 0x274
+#define MC_SMMU_VI_ASID 0x280
+#define MC_SMMU_VIC_ASID 0x284
+#define MC_SMMU_XUSB_HOST_ASID 0x288
+#define MC_SMMU_XUSB_DEV_ASID 0x28C
+#define MC_SMMU_A9AVP_ASID 0x290
+#define MC_SMMU_TSEC_ASID 0x294
+#define MC_SMMU_PPCS1_ASID 0x298
+#define MC_AHB_EXTRA_SNAP_LEVELS 0x2A0
+#define MC_APB_EXTRA_SNAP_LEVELS 0x2A4
+#define MC_AVP_EXTRA_SNAP_LEVELS 0x2A8
+#define MC_DIS_EXTRA_SNAP_LEVELS 0x2AC
+#define MC_PCX_EXTRA_SNAP_LEVELS 0x2B8
+#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2BC
+#define MC_SAX_EXTRA_SNAP_LEVELS 0x2C0
+#define MC_VE_EXTRA_SNAP_LEVELS 0x2D8
+#define MC_LATENCY_ALLOWANCE_AFI_0 0x2E0
+#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
+#define MC_LATENCY_ALLOWANCE_DC_0 0x2E8
+#define MC_LATENCY_ALLOWANCE_DC_1 0x2EC
+#define MC_LATENCY_ALLOWANCE_DC_2 0x2F0
+#define MC_LATENCY_ALLOWANCE_DCB_0 0x2F4
+#define MC_LATENCY_ALLOWANCE_DCB_1 0x2F8
+#define MC_LATENCY_ALLOWANCE_DCB_2 0x2FC
+#define MC_LATENCY_ALLOWANCE_HC_0 0x310
+#define MC_LATENCY_ALLOWANCE_HC_1 0x314
+#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
+#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
+#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
+#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
+#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
+#define MC_LATENCY_ALLOWANCE_PTC_0 0x34C
+#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
+#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
+#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
+#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
+#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
+#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
+#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
+#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
+#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
+#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
+#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3A0
+#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3A4
+#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
+#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
+#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
+#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
+#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
+#define MC_LATENCY_ALLOWANCE_DC_3 0x3C8
+#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
+#define MC_LATENCY_ALLOWANCE_APE_0 0x3DC
+#define MC_LATENCY_ALLOWANCE_SE_0 0x3E0
+#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3E4
+#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
+#define MC_LATENCY_ALLOWANCE_ETR_0 0x3EC
+#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3F0
+#define MC_RESERVED_RSV 0x3FC
+#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
+#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
+#define MC_MSE_EXTRA_SNAP_LEVELS 0x40C
+#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
+#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
+#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
+#define MC_DIS_PTSA_RATE 0x41C
+#define MC_DIS_PTSA_MIN 0x420
+#define MC_DIS_PTSA_MAX 0x424
+#define MC_DISB_PTSA_RATE 0x428
+#define MC_DISB_PTSA_MIN 0x42C
+#define MC_DISB_PTSA_MAX 0x430
+#define MC_VE_PTSA_RATE 0x434
+#define MC_VE_PTSA_MIN 0x438
+#define MC_VE_PTSA_MAX 0x43C
+#define MC_RING2_PTSA_RATE 0x440
+#define MC_RING2_PTSA_MIN 0x444
+#define MC_RING2_PTSA_MAX 0x448
+#define MC_MLL_MPCORER_PTSA_RATE 0x44C
+#define MC_MLL_MPCORER_PTSA_MIN 0x450
+#define MC_MLL_MPCORER_PTSA_MAX 0x454
+#define MC_SMMU_SMMU_PTSA_RATE 0x458
+#define MC_SMMU_SMMU_PTSA_MIN 0x45C
+#define MC_SMMU_SMMU_PTSA_MAX 0x460
+#define MC_RING1_PTSA_RATE 0x47C
+#define MC_RING1_PTSA_MIN 0x480
+#define MC_RING1_PTSA_MAX 0x484
+#define MC_A9AVPPC_PTSA_RATE 0x488
+#define MC_A9AVPPC_PTSA_MIN 0x48C
+#define MC_A9AVPPC_PTSA_MAX 0x490
+#define MC_VE2_PTSA_RATE 0x494
+#define MC_VE2_PTSA_MIN 0x498
+#define MC_VE2_PTSA_MAX 0x49C
+#define MC_ISP_PTSA_RATE 0x4A0
+#define MC_ISP_PTSA_MIN 0x4A4
+#define MC_ISP_PTSA_MAX 0x4A8
+#define MC_PCX_PTSA_RATE 0x4AC
+#define MC_PCX_PTSA_MIN 0x4B0
+#define MC_PCX_PTSA_MAX 0x4B4
+#define MC_SAX_PTSA_RATE 0x4B8
+#define MC_SAX_PTSA_MIN 0x4BC
+#define MC_SAX_PTSA_MAX 0x4C0
+#define MC_MSE_PTSA_RATE 0x4C4
+#define MC_MSE_PTSA_MIN 0x4C8
+#define MC_MSE_PTSA_MAX 0x4CC
+#define MC_SD_PTSA_RATE 0x4D0
+#define MC_SD_PTSA_MIN 0x4D4
+#define MC_SD_PTSA_MAX 0x4D8
+#define MC_AHB_PTSA_RATE 0x4DC
+#define MC_AHB_PTSA_MIN 0x4E0
+#define MC_AHB_PTSA_MAX 0x4E4
+#define MC_APB_PTSA_RATE 0x4E8
+#define MC_APB_PTSA_MIN 0x4EC
+#define MC_APB_PTSA_MAX 0x4F0
+#define MC_AVP_PTSA_RATE 0x4F4
+#define MC_AVP_PTSA_MIN 0x4F8
+#define MC_AVP_PTSA_MAX 0x4FC
+#define MC_FTOP_PTSA_RATE 0x50C
+#define MC_FTOP_PTSA_MIN 0x510
+#define MC_FTOP_PTSA_MAX 0x514
+#define MC_HOST_PTSA_RATE 0x518
+#define MC_HOST_PTSA_MIN 0x51C
+#define MC_HOST_PTSA_MAX 0x520
+#define MC_USBX_PTSA_RATE 0x524
+#define MC_USBX_PTSA_MIN 0x528
+#define MC_USBX_PTSA_MAX 0x52C
+#define MC_USBD_PTSA_RATE 0x530
+#define MC_USBD_PTSA_MIN 0x534
+#define MC_USBD_PTSA_MAX 0x538
+#define MC_GK_PTSA_RATE 0x53C
+#define MC_GK_PTSA_MIN 0x540
+#define MC_GK_PTSA_MAX 0x544
+#define MC_AUD_PTSA_RATE 0x548
+#define MC_AUD_PTSA_MIN 0x54C
+#define MC_AUD_PTSA_MAX 0x550
+#define MC_VICPC_PTSA_RATE 0x554
+#define MC_VICPC_PTSA_MIN 0x558
+#define MC_VICPC_PTSA_MAX 0x55C
+#define MC_JPG_PTSA_RATE 0x584
+#define MC_JPG_PTSA_MIN 0x588
+#define MC_JPG_PTSA_MAX 0x58C
+#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
+#define MC_SMMU_TLB_SET_SELECTION_MASK_0 0x600
+#define MC_GK2_PTSA_RATE 0x610
+#define MC_GK2_PTSA_MIN 0x614
+#define MC_GK2_PTSA_MAX 0x618
+#define MC_SDM_PTSA_RATE 0x61C
+#define MC_SDM_PTSA_MIN 0x620
+#define MC_SDM_PTSA_MAX 0x624
+#define MC_HDAPC_PTSA_RATE 0x628
+#define MC_HDAPC_PTSA_MIN 0x62C
+#define MC_HDAPC_PTSA_MAX 0x630
+#define MC_DFD_PTSA_RATE 0x634
+#define MC_DFD_PTSA_MIN 0x638
+#define MC_DFD_PTSA_MAX 0x63C
+#define MC_VIDEO_PROTECT_BOM 0x648
+#define MC_VIDEO_PROTECT_SIZE_MB 0x64C
+#define MC_VIDEO_PROTECT_REG_CTRL 0x650
+#define MC_ERR_VPR_STATUS 0x654
+#define MC_ERR_VPR_ADR 0x658
+#define MC_IRAM_BOM 0x65C
+#define MC_IRAM_TOM 0x660
+#define MC_EMEM_CFG_ACCESS_CTRL 0x664
+#define MC_TZ_SECURITY_CTRL 0x668
+#define TZ_SEC_CTRL_CPU_STRICT_TZ_APERTURE_CHECK BIT(0)
+#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66C
+#define MC_SEC_CARVEOUT_BOM 0x670
+#define MC_SEC_CARVEOUT_SIZE_MB 0x674
+#define MC_SEC_CARVEOUT_REG_CTRL 0x678
+#define MC_ERR_SEC_STATUS 0x67C
+#define MC_ERR_SEC_ADR 0x680
+#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
+#define MC_STUTTER_CONTROL 0x688
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69C
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6A0
+#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6A4
+#define MC_EMEM_ARB_NISO_THROTTLE 0x6B0
+#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6B4
+#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6B8
+#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6BC
+#define MC_EMEM_ARB_TIMING_RFCPB 0x6C0
+#define MC_EMEM_ARB_TIMING_CCDMW 0x6C4
+#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6F0
+#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6F4
+#define MC_MIN_LENGTH_AFI_0 0x88C
+#define MC_MIN_LENGTH_AVPC_0 0x890
+#define MC_MIN_LENGTH_DC_0 0x894
+#define MC_MIN_LENGTH_DC_1 0x898
+#define MC_MIN_LENGTH_DC_2 0x89C
+#define MC_MIN_LENGTH_DCB_0 0x8A0
+#define MC_MIN_LENGTH_DCB_1 0x8A4
+#define MC_MIN_LENGTH_DCB_2 0x8A8
+#define MC_MIN_LENGTH_HC_0 0x8BC
+#define MC_MIN_LENGTH_HC_1 0x8C0
+#define MC_MIN_LENGTH_HDA_0 0x8C4
+#define MC_MIN_LENGTH_MPCORE_0 0x8CC
+#define MC_MIN_LENGTH_NVENC_0 0x8D4
+#define MC_MIN_LENGTH_PPCS_0 0x8F0
+#define MC_MIN_LENGTH_PPCS_1 0x8F4
+#define MC_MIN_LENGTH_PTC_0 0x8F8
+#define MC_MIN_LENGTH_SATA_0 0x8FC
+#define MC_MIN_LENGTH_ISP2_0 0x91C
+#define MC_MIN_LENGTH_ISP2_1 0x920
+#define MC_MIN_LENGTH_XUSB_0 0x928
+#define MC_MIN_LENGTH_XUSB_1 0x92C
+#define MC_MIN_LENGTH_ISP2B_0 0x930
+#define MC_MIN_LENGTH_ISP2B_1 0x934
+#define MC_MIN_LENGTH_TSEC_0 0x93C
+#define MC_MIN_LENGTH_VIC_0 0x940
+#define MC_MIN_LENGTH_VI2_0 0x944
+#define MC_MIN_LENGTH_AXIAP_0 0x94C
+#define MC_MIN_LENGTH_A9AVP_0 0x950
+#define MC_RESERVED_RSV_1 0x958
+#define MC_DVFS_PIPE_SELECT 0x95C
+#define MC_PTSA_GRANT_DECREMENT 0x960
+#define MC_IRAM_REG_CTRL 0x964
+#define MC_EMEM_ARB_OVERRIDE_1 0x968
+#define MC_CLIENT_HOTRESET_CTRL_1 0x970
+#define MC_CLIENT_HOTRESET_STATUS_1 0x974
+#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
+#define MC_IRAM_ADR_HI 0x980
+#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
+#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
+#define MC_EMEM_ARB_STATS_0 0x990
+#define MC_EMEM_ARB_STATS_1 0x994
+#define MC_MTS_CARVEOUT_BOM 0x9A0
+#define MC_MTS_CARVEOUT_SIZE_MB 0x9A4
+#define MC_MTS_CARVEOUT_ADR_HI 0x9A8
+#define MC_MTS_CARVEOUT_REG_CTRL 0x9AC
+#define MC_ERR_MTS_STATUS 0x9B0
+#define MC_ERR_MTS_ADR 0x9B4
+#define MC_SMMU_PTC_FLUSH_1 0x9B8
+#define MC_SECURITY_CFG3 0x9BC
+#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9D0
+#define MC_SEC_CARVEOUT_ADR_HI 0x9D4
+#define MC_DA_CONFIG0 0x9DC
+#define MC_SMMU_ASID_SECURITY_2 0x9E0
+#define MC_SMMU_ASID_SECURITY_3 0x9E4
+#define MC_SMMU_ASID_SECURITY_4 0x9E8
+#define MC_SMMU_ASID_SECURITY_5 0x9EC
+#define MC_SMMU_ASID_SECURITY_6 0x9F0
+#define MC_SMMU_ASID_SECURITY_7 0x9F4
+#define MC_GK_EXTRA_SNAP_LEVELS 0xA00
+#define MC_SD_EXTRA_SNAP_LEVELS 0xA04
+#define MC_ISP_EXTRA_SNAP_LEVELS 0xA08
+#define MC_AUD_EXTRA_SNAP_LEVELS 0xA10
+#define MC_HOST_EXTRA_SNAP_LEVELS 0xA14
+#define MC_USBD_EXTRA_SNAP_LEVELS 0xA18
+#define MC_VICPC_EXTRA_SNAP_LEVELS 0xA1C
+#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xA20
+#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xA24
+#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xA28
+#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xA2C
+#define MC_JPG_EXTRA_SNAP_LEVELS 0xA3C
+#define MC_GK2_EXTRA_SNAP_LEVELS 0xA40
+#define MC_SDM_EXTRA_SNAP_LEVELS 0xA44
+#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xA48
+#define MC_DFD_EXTRA_SNAP_LEVELS 0xA4C
+#define MC_SMMU_DC1_ASID 0xA88
+#define MC_SMMU_SDMMC1A_ASID 0xA94
+#define MC_SMMU_SDMMC2A_ASID 0xA98
+#define MC_SMMU_SDMMC3A_ASID 0xA9C
+#define MC_SMMU_SDMMC4A_ASID 0xAA0
+#define MC_SMMU_ISP2B_ASID 0xAA4
+#define MC_SMMU_GPU_ASID 0xAA8
+#define MC_SMMU_GPUB_ASID 0xAAC
+#define MC_SMMU_PPCS2_ASID 0xAB0
+#define MC_SMMU_NVDEC_ASID 0xAB4
+#define MC_SMMU_APE_ASID 0xAB8
+#define MC_SMMU_SE_ASID 0xABC
+#define MC_SMMU_NVJPG_ASID 0xAC0
+#define MC_SMMU_HC1_ASID 0xAC4
+#define MC_SMMU_SE1_ASID 0xAC8
+#define MC_SMMU_AXIAP_ASID 0xACC
+#define MC_SMMU_ETR_ASID 0xAD0
+#define MC_SMMU_TSECB_ASID 0xAD4
+#define MC_SMMU_TSEC1_ASID 0xAD8
+#define MC_SMMU_TSECB1_ASID 0xADC
+#define MC_SMMU_NVDEC1_ASID 0xAE0
+#define MC_MIN_LENGTH_GPU_0 0xB04
+#define MC_MIN_LENGTH_SDMMCA_0 0xB10
+#define MC_MIN_LENGTH_SDMMCAA_0 0xB14
+#define MC_MIN_LENGTH_SDMMC_0 0xB18
+#define MC_MIN_LENGTH_SDMMCAB_0 0xB1C
+#define MC_MIN_LENGTH_DC_3 0xB20
+#define MC_MIN_LENGTH_NVDEC_0 0xB30
+#define MC_MIN_LENGTH_APE_0 0xB34
+#define MC_MIN_LENGTH_SE_0 0xB38
+#define MC_MIN_LENGTH_NVJPG_0 0xB3C
+#define MC_MIN_LENGTH_GPU2_0 0xB40
+#define MC_MIN_LENGTH_ETR_0 0xB44
+#define MC_MIN_LENGTH_TSECB_0 0xB48
+#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xB80
+#define MC_EMEM_ARB_HYSTERESIS_4 0xB84
+#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xB88
+#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xB8C
+#define MC_EMEM_ARB_ISOCHRONOUS_4 0xB94
+#define MC_SMMU_TRANSLATION_ENABLE_4 0xB98
+#define MC_SMMU_CLIENT_CONFIG4 0xB9C
+#define MC_EMEM_ARB_DHYSTERESIS_0 0xBB0
+#define MC_EMEM_ARB_DHYSTERESIS_1 0xBB4
+#define MC_EMEM_ARB_DHYSTERESIS_2 0xBB8
+#define MC_EMEM_ARB_DHYSTERESIS_3 0xBBC
+#define MC_EMEM_ARB_DHYSTERESIS_4 0xBC0
+#define MC_EMEM_ARB_DHYST_CTRL 0xBCC
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
+#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
+#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xC00
+#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xC04
+#define MC_SECURITY_CARVEOUT1_CFG0 0xC08
+#define MC_SECURITY_CARVEOUT1_BOM 0xC0C
+#define MC_SECURITY_CARVEOUT1_BOM_HI 0xC10
+#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xC14
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xC18
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xC1C
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xC20
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xC24
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xC28
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xC2C
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xC30
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xC34
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xC38
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xC3C
+#define MC_SECURITY_CARVEOUT2_CFG0 0xC58
+#define MC_SECURITY_CARVEOUT2_BOM 0xC5C
+#define MC_SECURITY_CARVEOUT2_BOM_HI 0xC60
+#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xC64
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xC68
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xC6C
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xC70
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xC74
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xC78
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xC7C
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xC80
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xC84
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xC88
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xC8C
+#define MC_SECURITY_CARVEOUT3_CFG0 0xCA8
+#define MC_SECURITY_CARVEOUT3_BOM 0xCAC
+#define MC_SECURITY_CARVEOUT3_BOM_HI 0xCB0
+#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xCB4
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xCB8
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xCBC
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xCC0
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xCC4
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xCC8
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xCCC
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xCD0
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xCD4
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xCD8
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xCDC
+#define MC_SECURITY_CARVEOUT4_CFG0 0xCF8
+#define MC_SECURITY_CARVEOUT4_BOM 0xCFC
+#define MC_SECURITY_CARVEOUT4_BOM_HI 0xD00
+#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xD04
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xD08
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xD0C
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xD10
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xD14
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xD18
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xD1C
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xD20
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xD24
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xD28
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xD2C
+#define MC_SECURITY_CARVEOUT5_CFG0 0xD48
+#define MC_SECURITY_CARVEOUT5_BOM 0xD4C
+#define MC_SECURITY_CARVEOUT5_BOM_HI 0xD50
+#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xD54
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xD58
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xD5C
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xD60
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xD64
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xD68
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xD6C
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xD70
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xD74
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xD78
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xD7C
+#define MC_PCFIFO_CLIENT_CONFIG0 0xDD0
+#define MC_PCFIFO_CLIENT_CONFIG1 0xDD4
+#define MC_PCFIFO_CLIENT_CONFIG2 0xDD8
+#define MC_PCFIFO_CLIENT_CONFIG3 0xDDC
+#define MC_PCFIFO_CLIENT_CONFIG4 0xDE0
-/*! MC General registers */
-#define MC_INTSTATUS 0x0
-#define MC_INTMASK 0x4
-#define MC_ERR_STATUS 0x8
-#define MC_ERR_ADR 0xc
-#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
-#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
-#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
-#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
-#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
-#define MC_EMEM_CFG 0x50
-#define MC_EMEM_ADR_CFG 0x54
-#define MC_EMEM_ADR_CFG_DEV0 0x58
-#define MC_EMEM_ADR_CFG_DEV1 0x5c
-#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
-#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
-#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
-#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
-#define MC_SECURITY_CFG0 0x70
-#define MC_SECURITY_CFG1 0x74
-#define MC_SECURITY_CFG3 0x9bc
-#define MC_SECURITY_RSV 0x7c
-#define MC_EMEM_ARB_CFG 0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
-#define MC_EMEM_ARB_TIMING_RCD 0x98
-#define MC_EMEM_ARB_TIMING_RP 0x9c
-#define MC_EMEM_ARB_TIMING_RC 0xa0
-#define MC_EMEM_ARB_TIMING_RAS 0xa4
-#define MC_EMEM_ARB_TIMING_FAW 0xa8
-#define MC_EMEM_ARB_TIMING_RRD 0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
-#define MC_EMEM_ARB_TIMING_R2R 0xb8
-#define MC_EMEM_ARB_TIMING_W2W 0xbc
-#define MC_EMEM_ARB_TIMING_R2W 0xc0
-#define MC_EMEM_ARB_TIMING_W2R 0xc4
-#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
-#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
-#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
-#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
-#define MC_EMEM_ARB_DA_TURNS 0xd0
-#define MC_EMEM_ARB_DA_COVERS 0xd4
-#define MC_EMEM_ARB_MISC0 0xd8
-#define MC_EMEM_ARB_MISC1 0xdc
-#define MC_EMEM_ARB_MISC2 0xc8
-#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
-#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
-#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
-#define MC_EMEM_ARB_OVERRIDE 0xe8
-#define MC_EMEM_ARB_RSV 0xec
-#define MC_CLKEN_OVERRIDE 0xf4
-#define MC_TIMING_CONTROL_DBG 0xf8
-#define MC_TIMING_CONTROL 0xfc
-#define MC_STAT_CONTROL 0x100
-#define MC_STAT_STATUS 0x104
-#define MC_STAT_EMC_CLOCK_LIMIT 0x108
-#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
-#define MC_STAT_EMC_CLOCKS 0x110
-#define MC_STAT_EMC_CLOCKS_MSBS 0x114
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
-#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
-#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
-#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
-#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
-#define MC_STAT_EMC_SET0_COUNT 0x138
-#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
-#define MC_STAT_EMC_SET1_COUNT 0x178
-#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
-#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
-#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
-#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
-#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
-#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
-#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
-#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
-#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
-#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
-#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
-#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
-#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
-#define MC_CLIENT_HOTRESET_CTRL 0x200
-#define MC_CLIENT_HOTRESET_CTRL_1 0x970
-#define MC_CLIENT_HOTRESET_STATUS 0x204
-#define MC_CLIENT_HOTRESET_STATUS_1 0x974
-#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
-#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
-#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
-#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
-#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
-#define MC_EMEM_ARB_HYSTERESIS_0 0x218
-#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
-#define MC_EMEM_ARB_HYSTERESIS_2 0x220
-#define MC_EMEM_ARB_HYSTERESIS_3 0x224
-#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
-#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
-#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
-#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
-#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
-#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
-#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
-#define MC_RESERVED_RSV 0x3fc
-#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
-#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
-#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0
-#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
-#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
-#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
-#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
-#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40
-#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
-#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
-#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
-#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
-#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
-#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
-#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
-#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
-#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8
-#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
-#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8
-#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
-#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c
-#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
-#define MC_GK_EXTRA_SNAP_LEVELS 0xa00
-#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
-#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
-#define MC_VIDEO_PROTECT_BOM 0x648
-#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
-#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
-#define MC_VIDEO_PROTECT_REG_CTRL 0x650
-#define MC_ERR_VPR_STATUS 0x654
-#define MC_ERR_VPR_ADR 0x658
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
-#define MC_IRAM_BOM 0x65c
-#define MC_IRAM_TOM 0x660
-#define MC_IRAM_ADR_HI 0x980
-#define MC_IRAM_REG_CTRL 0x964
-#define MC_EMEM_CFG_ACCESS_CTRL 0x664
-#define MC_TZ_SECURITY_CTRL 0x668
-#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
-#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
-#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
-#define MC_SEC_CARVEOUT_BOM 0x670
-#define MC_SEC_CARVEOUT_SIZE_MB 0x674
-#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
-#define MC_SEC_CARVEOUT_REG_CTRL 0x678
-#define MC_ERR_SEC_STATUS 0x67c
-#define MC_ERR_SEC_ADR 0x680
-#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
-#define MC_STUTTER_CONTROL 0x688
-#define MC_RESERVED_RSV_1 0x958
-#define MC_DVFS_PIPE_SELECT 0x95c
-#define MC_AHB_PTSA_MIN 0x4e0
-#define MC_AUD_PTSA_MIN 0x54c
-#define MC_MLL_MPCORER_PTSA_RATE 0x44c
-#define MC_RING2_PTSA_RATE 0x440
-#define MC_USBD_PTSA_RATE 0x530
-#define MC_USBX_PTSA_MIN 0x528
-#define MC_USBD_PTSA_MIN 0x534
-#define MC_APB_PTSA_MAX 0x4f0
-#define MC_JPG_PTSA_RATE 0x584
-#define MC_DIS_PTSA_MIN 0x420
-#define MC_AVP_PTSA_MAX 0x4fc
-#define MC_AVP_PTSA_RATE 0x4f4
-#define MC_RING1_PTSA_MIN 0x480
-#define MC_DIS_PTSA_MAX 0x424
-#define MC_SD_PTSA_MAX 0x4d8
-#define MC_MSE_PTSA_RATE 0x4c4
-#define MC_VICPC_PTSA_MIN 0x558
-#define MC_PCX_PTSA_MAX 0x4b4
-#define MC_ISP_PTSA_RATE 0x4a0
-#define MC_A9AVPPC_PTSA_MIN 0x48c
-#define MC_RING2_PTSA_MAX 0x448
-#define MC_AUD_PTSA_RATE 0x548
-#define MC_HOST_PTSA_MIN 0x51c
-#define MC_MLL_MPCORER_PTSA_MAX 0x454
-#define MC_SD_PTSA_MIN 0x4d4
-#define MC_RING1_PTSA_RATE 0x47c
-#define MC_JPG_PTSA_MIN 0x588
-#define MC_HDAPC_PTSA_MIN 0x62c
-#define MC_AVP_PTSA_MIN 0x4f8
-#define MC_JPG_PTSA_MAX 0x58c
-#define MC_VE_PTSA_MAX 0x43c
-#define MC_DFD_PTSA_MAX 0x63c
-#define MC_VICPC_PTSA_RATE 0x554
-#define MC_GK_PTSA_MAX 0x544
-#define MC_VICPC_PTSA_MAX 0x55c
-#define MC_SDM_PTSA_MAX 0x624
-#define MC_SAX_PTSA_RATE 0x4b8
-#define MC_PCX_PTSA_MIN 0x4b0
-#define MC_APB_PTSA_MIN 0x4ec
-#define MC_GK2_PTSA_MIN 0x614
-#define MC_PCX_PTSA_RATE 0x4ac
-#define MC_RING1_PTSA_MAX 0x484
-#define MC_HDAPC_PTSA_RATE 0x628
-#define MC_MLL_MPCORER_PTSA_MIN 0x450
-#define MC_GK2_PTSA_MAX 0x618
-#define MC_AUD_PTSA_MAX 0x550
-#define MC_GK2_PTSA_RATE 0x610
-#define MC_ISP_PTSA_MAX 0x4a8
-#define MC_DISB_PTSA_RATE 0x428
-#define MC_VE2_PTSA_MAX 0x49c
-#define MC_DFD_PTSA_MIN 0x638
-#define MC_FTOP_PTSA_RATE 0x50c
-#define MC_A9AVPPC_PTSA_RATE 0x488
-#define MC_VE2_PTSA_MIN 0x498
-#define MC_USBX_PTSA_MAX 0x52c
-#define MC_DIS_PTSA_RATE 0x41c
-#define MC_USBD_PTSA_MAX 0x538
-#define MC_A9AVPPC_PTSA_MAX 0x490
-#define MC_USBX_PTSA_RATE 0x524
-#define MC_FTOP_PTSA_MAX 0x514
-#define MC_HDAPC_PTSA_MAX 0x630
-#define MC_SD_PTSA_RATE 0x4d0
-#define MC_DFD_PTSA_RATE 0x634
-#define MC_FTOP_PTSA_MIN 0x510
-#define MC_SDM_PTSA_RATE 0x61c
-#define MC_AHB_PTSA_RATE 0x4dc
-#define MC_SMMU_SMMU_PTSA_MAX 0x460
-#define MC_RING2_PTSA_MIN 0x444
-#define MC_SDM_PTSA_MIN 0x620
-#define MC_APB_PTSA_RATE 0x4e8
-#define MC_MSE_PTSA_MIN 0x4c8
-#define MC_HOST_PTSA_RATE 0x518
-#define MC_VE_PTSA_RATE 0x434
-#define MC_AHB_PTSA_MAX 0x4e4
-#define MC_SAX_PTSA_MIN 0x4bc
-#define MC_SMMU_SMMU_PTSA_MIN 0x45c
-#define MC_ISP_PTSA_MIN 0x4a4
-#define MC_HOST_PTSA_MAX 0x520
-#define MC_SAX_PTSA_MAX 0x4c0
-#define MC_VE_PTSA_MIN 0x438
-#define MC_GK_PTSA_MIN 0x540
-#define MC_MSE_PTSA_MAX 0x4cc
-#define MC_DISB_PTSA_MAX 0x430
-#define MC_DISB_PTSA_MIN 0x42c
-#define MC_SMMU_SMMU_PTSA_RATE 0x458
-#define MC_VE2_PTSA_RATE 0x494
-#define MC_GK_PTSA_RATE 0x53c
-#define MC_PTSA_GRANT_DECREMENT 0x960
-#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
-#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
-#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
-#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
-#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
-#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
-#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
-#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
-#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
-#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
-#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
-#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
-#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
-#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
-#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
-#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
-#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
-#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
-#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
-#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
-#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
-#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
-#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
-#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
-#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
-#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
-#define MC_LATENCY_ALLOWANCE_HC_1 0x314
-#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
-#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
-#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
-#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
-#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
-#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
-#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
-#define MC_LATENCY_ALLOWANCE_HC_0 0x310
-#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
-#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
-#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
-#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
-#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
-#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
-#define MC_MIN_LENGTH_APE_0 0xb34
-#define MC_MIN_LENGTH_DCB_2 0x8a8
-#define MC_MIN_LENGTH_A9AVP_0 0x950
-#define MC_MIN_LENGTH_TSEC_0 0x93c
-#define MC_MIN_LENGTH_DC_1 0x898
-#define MC_MIN_LENGTH_AXIAP_0 0x94c
-#define MC_MIN_LENGTH_ISP2B_0 0x930
-#define MC_MIN_LENGTH_VI2_0 0x944
-#define MC_MIN_LENGTH_DCB_0 0x8a0
-#define MC_MIN_LENGTH_DCB_1 0x8a4
-#define MC_MIN_LENGTH_PPCS_1 0x8f4
-#define MC_MIN_LENGTH_NVJPG_0 0xb3c
-#define MC_MIN_LENGTH_HDA_0 0x8c4
-#define MC_MIN_LENGTH_NVENC_0 0x8d4
-#define MC_MIN_LENGTH_SDMMC_0 0xb18
-#define MC_MIN_LENGTH_ISP2B_1 0x934
-#define MC_MIN_LENGTH_HC_1 0x8c0
-#define MC_MIN_LENGTH_DC_3 0xb20
-#define MC_MIN_LENGTH_AVPC_0 0x890
-#define MC_MIN_LENGTH_VIC_0 0x940
-#define MC_MIN_LENGTH_ISP2_0 0x91c
-#define MC_MIN_LENGTH_HC_0 0x8bc
-#define MC_MIN_LENGTH_SE_0 0xb38
-#define MC_MIN_LENGTH_NVDEC_0 0xb30
-#define MC_MIN_LENGTH_SATA_0 0x8fc
-#define MC_MIN_LENGTH_DC_0 0x894
-#define MC_MIN_LENGTH_XUSB_1 0x92c
-#define MC_MIN_LENGTH_DC_2 0x89c
-#define MC_MIN_LENGTH_SDMMCAA_0 0xb14
-#define MC_MIN_LENGTH_GPU_0 0xb04
-#define MC_MIN_LENGTH_ETR_0 0xb44
-#define MC_MIN_LENGTH_AFI_0 0x88c
-#define MC_MIN_LENGTH_PPCS_0 0x8f0
-#define MC_MIN_LENGTH_ISP2_1 0x920
-#define MC_MIN_LENGTH_XUSB_0 0x928
-#define MC_MIN_LENGTH_MPCORE_0 0x8cc
-#define MC_MIN_LENGTH_TSECB_0 0xb48
-#define MC_MIN_LENGTH_SDMMCA_0 0xb10
-#define MC_MIN_LENGTH_GPU2_0 0xb40
-#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c
-#define MC_MIN_LENGTH_PTC_0 0x8f8
-#define MC_EMEM_ARB_OVERRIDE_1 0x968
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
-#define MC_EMEM_ARB_STATS_0 0x990
-#define MC_EMEM_ARB_STATS_1 0x994
-#define MC_MTS_CARVEOUT_BOM 0x9a0
-#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
-#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
-#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
-#define MC_ERR_MTS_STATUS 0x9b0
-#define MC_ERR_MTS_ADR 0x9b4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74
-#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
-#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c
-#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
-#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
-#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
-#define MC_SECURITY_CARVEOUT3_BOM 0xcac
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
-#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88
-#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
-#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
-#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
-#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
-#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8
-#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
-#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80
-#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc
-#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
-#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
-#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
-#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0
-#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
-#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
-#define MC_UNTRANSLATED_REGION_CHECK 0x948
-#define MC_DA_CONFIG0 0x9dc
+/* T210B01 only registers */
+#define MC_SMMU_ISP21_ASID_B01 0x804
+#define MC_SMMU_ISP2B1_ASID_B01 0x808
+#define MC_UNTRANSLATED_REGION_CHECK_B01 0x948
-/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_ACCESS/CLIENT_FORCE_INTERNAL_ACCESS0 */
#define SEC_CARVEOUT_CA0_R_PTCR BIT(0)
#define SEC_CARVEOUT_CA0_R_DISPLAY0A BIT(1)
#define SEC_CARVEOUT_CA0_R_DISPLAY0AB BIT(2)
@@ -501,7 +563,7 @@
#define SEC_CARVEOUT_CA0_R_PPCSAHBSLV BIT(30)
#define SEC_CARVEOUT_CA0_R_SATAR BIT(31)
-/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_ACCESS/CLIENT_FORCE_INTERNAL_ACCESS1 */
#define SEC_CARVEOUT_CA1_R_VDEBSEV BIT(2)
#define SEC_CARVEOUT_CA1_R_VDEMBE BIT(3)
#define SEC_CARVEOUT_CA1_R_VDEMCE BIT(4)
@@ -521,7 +583,7 @@
#define SEC_CARVEOUT_CA1_W_VDEBSEV BIT(30)
#define SEC_CARVEOUT_CA1_W_VDEDBG BIT(31)
-/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_ACCESS/CLIENT_FORCE_INTERNAL_ACCESS2 */
#define SEC_CARVEOUT_CA2_W_VDEMBE BIT(0)
#define SEC_CARVEOUT_CA2_W_VDETPM BIT(1)
#define SEC_CARVEOUT_CA2_R_ISPRA BIT(4)
@@ -541,7 +603,7 @@
#define SEC_CARVEOUT_CA2_W_GPU BIT(25)
#define SEC_CARVEOUT_CA2_R_DISPLAYT BIT(26)
-/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_ACCESS/CLIENT_FORCE_INTERNAL_ACCESS3 */
#define SEC_CARVEOUT_CA3_R_SDMMCA BIT(0)
#define SEC_CARVEOUT_CA3_R_SDMMCAA BIT(1)
#define SEC_CARVEOUT_CA3_R_SDMMC BIT(2)
@@ -561,7 +623,7 @@
#define SEC_CARVEOUT_CA3_R_NVJPG BIT(30)
#define SEC_CARVEOUT_CA3_W_NVJPG BIT(31)
-/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_ACCESS/CLIENT_FORCE_INTERNAL_ACCESS4 */
#define SEC_CARVEOUT_CA4_R_SE BIT(0)
#define SEC_CARVEOUT_CA4_W_SE BIT(1)
#define SEC_CARVEOUT_CA4_R_AXIAP BIT(2)
@@ -573,7 +635,7 @@
#define SEC_CARVEOUT_CA4_R_GPU2 BIT(8)
#define SEC_CARVEOUT_CA4_W_GPU2 BIT(9)
-// MC_VIDEO_PROTECT_REG_CTRL
+/*! MC_VIDEO_PROTECT_REG_CTRL */
#define VPR_LOCK_MODE_SHIFT 0
#define VPR_CTRL_UNLOCKED (0 << VPR_LOCK_MODE_SHIFT)
#define VPR_CTRL_LOCKED (1 << VPR_LOCK_MODE_SHIFT)
@@ -581,7 +643,7 @@
#define SEC_CTRL_SECURE (0 << VPR_PROTECT_MODE_SHIFT)
#define VPR_CTRL_TZ_SECURE (1 << VPR_PROTECT_MODE_SHIFT)
-// MC_SECURITY_CARVEOUTX_CFG0
+/*! MC_SECURITY_CARVEOUTX_CFG0 */
// Mode of LOCK_MODE.
#define PROTECT_MODE_SHIFT 0
#define SEC_CARVEOUT_CFG_ALL_SECURE (0 << PROTECT_MODE_SHIFT)
@@ -632,4 +694,652 @@
#define SEC_CARVEOUT_CFG_IS_WPR BIT(27)
+// WPR1 magic to enable WPR2.
+#define ACR_GSC3_ENABLE_MAGIC 0xC0EDBBCC
+
+/*! MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+// VPR CYA. Parsed as (vpr_gpu_ovr1 << 32 | vpr_gpu_ovr0) << 5.
+#define VPR_TRUST_UNTRUSTED 0
+#define VPR_TRUST_GRAPHICS 1
+#define VPR_TRUST_QUARANTINE 2
+#define VPR_TRUST_TRUSTED 3
+// VPR CYA LO.
+// Setting VPR_OVR0_CYA_TRUST_DEFAULT disables the overrides.
+// Defaults: PD, SCC, SKED, L1, TEX, PE, RASTER, GCC and PROP as GRAPHICS. The rest UNTRUSTED.
+#define VPR_OVR0_CYA_TRUST_OVERRIDE 0
+#define VPR_OVR0_CYA_TRUST_DEFAULT BIT(0)
+#define VPR_OVR0_CYA_TRUST_CPU(t) ((t) << 1u) // HOST CPU.
+#define VPR_OVR0_CYA_TRUST_HOST(t) ((t) << 3u)
+#define VPR_OVR0_CYA_TRUST_PERF(t) ((t) << 5u)
+#define VPR_OVR0_CYA_TRUST_PMU(t) ((t) << 7u)
+#define VPR_OVR0_CYA_TRUST_CE2(t) ((t) << 9u) // GRCOPY.
+#define VPR_OVR0_CYA_TRUST_SEC(t) ((t) << 11u)
+#define VPR_OVR0_CYA_TRUST_FE(t) ((t) << 13u)
+#define VPR_OVR0_CYA_TRUST_PD(t) ((t) << 15u)
+#define VPR_OVR0_CYA_TRUST_SCC(t) ((t) << 17u)
+#define VPR_OVR0_CYA_TRUST_SKED(t) ((t) << 19u)
+#define VPR_OVR0_CYA_TRUST_L1(t) ((t) << 21u)
+#define VPR_OVR0_CYA_TRUST_TEX(t) ((t) << 23u)
+#define VPR_OVR0_CYA_TRUST_PE(t) ((t) << 25u)
+// VPR CYA HI.
+#define VPR_OVR0_CYA_TRUST_RASTER(t) ((t) << 27u)
+#define VPR_OVR0_CYA_TRUST_GCC(t) ((t) << 29u)
+// Setting GPCCS to anything other than untrusted, causes a hang.
+#define VPR_OVR0_CYA_TRUST_GPCCS(t) (((t) & 1) << 31u)
+
+/*! MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+// VPR CYA HI.
+#define VPR_OVR1_CYA_TRUST_GPCCS(t) ((t) >> 1)
+#define VPR_OVR1_CYA_TRUST_PROP(t) ((t) << 1u)
+#define VPR_OVR1_CYA_TRUST_PROP_READ BIT(3)
+#define VPR_OVR1_CYA_TRUST_PROP_WRITE BIT(4)
+#define VPR_OVR1_CYA_TRUST_DNISO(t) ((t) << 5u)
+#define VPR_OVR1_CYA_TRUST_CE0(t) VPR_OVR1_CYA_TRUST_DNISO(t)
+#define VPR_OVR1_CYA_TRUST_CE1(t) VPR_OVR1_CYA_TRUST_DNISO(t)
+#define VPR_OVR1_CYA_TRUST_NVENC(t) ((t) << 7u) // Unused?
+#define VPR_OVR1_CYA_TRUST_NVDEC(t) ((t) << 9u) // Unused?
+#define VPR_OVR1_CYA_TRUST_MSPPP(t) ((t) << 11u) // Unused? VIC/JPG?
+#define VPR_OVR1_CYA_TRUST_MSVLD(t) ((t) << 13u) // Unused? SEC2?
+
+typedef struct _mc_regs_t210_t {
+/* 0x000 */ u32 mc_intstatus;
+/* 0x004 */ u32 mc_intmask;
+/* 0x008 */ u32 mc_err_status;
+/* 0x00c */ u32 mc_err_adr;
+/* 0x010 */ u32 mc_smmu_config;
+/* 0x014 */ u32 mc_smmu_tlb_config;
+/* 0x018 */ u32 mc_smmu_ptc_config;
+/* 0x01c */ u32 mc_smmu_ptb_asid;
+/* 0x020 */ u32 mc_smmu_ptb_data;
+/* 0x024 */ u32 mc_rsvd_24[3];
+/* 0x030 */ u32 mc_smmu_tlb_flush;
+/* 0x034 */ u32 mc_smmu_ptc_flush;
+/* 0x038 */ u32 mc_smmu_asid_security;
+/* 0x03c */ u32 mc_smmu_asid_security_1;
+/* 0x040 */ u32 mc_smmu_client_config0;
+/* 0x044 */ u32 mc_smmu_client_config1;
+/* 0x048 */ u32 mc_smmu_client_config2;
+/* 0x04c */ u32 mc_smmu_client_config3;
+/* 0x050 */ u32 mc_emem_cfg;
+/* 0x054 */ u32 mc_emem_adr_cfg;
+/* 0x058 */ u32 mc_emem_adr_cfg_dev0;
+/* 0x05c */ u32 mc_emem_adr_cfg_dev1;
+/* 0x060 */ u32 mc_emem_adr_cfg_channel_mask;
+/* 0x064 */ u32 mc_emem_adr_cfg_bank_mask_0;
+/* 0x068 */ u32 mc_emem_adr_cfg_bank_mask_1;
+/* 0x06c */ u32 mc_emem_adr_cfg_bank_mask_2;
+/* 0x070 */ u32 mc_security_cfg0;
+/* 0x074 */ u32 mc_security_cfg1;
+/* 0x078 */ u32 mc_rsvd_78;
+/* 0x07c */ u32 mc_security_rsv;
+/* 0x080 */ u32 mc_rsvd_80[4];
+/* 0x090 */ u32 mc_emem_arb_cfg;
+/* 0x094 */ u32 mc_emem_arb_outstanding_req;
+/* 0x098 */ u32 mc_emem_arb_timing_rcd;
+/* 0x09c */ u32 mc_emem_arb_timing_rp;
+/* 0x0a0 */ u32 mc_emem_arb_timing_rc;
+/* 0x0a4 */ u32 mc_emem_arb_timing_ras;
+/* 0x0a8 */ u32 mc_emem_arb_timing_faw;
+/* 0x0ac */ u32 mc_emem_arb_timing_rrd;
+/* 0x0b0 */ u32 mc_emem_arb_timing_rap2pre;
+/* 0x0b4 */ u32 mc_emem_arb_timing_wap2pre;
+/* 0x0b8 */ u32 mc_emem_arb_timing_r2r;
+/* 0x0bc */ u32 mc_emem_arb_timing_w2w;
+/* 0x0c0 */ u32 mc_emem_arb_timing_r2w;
+/* 0x0c4 */ u32 mc_emem_arb_timing_w2r;
+/* 0x0c8 */ u32 mc_emem_arb_misc2;
+/* 0x0cc */ u32 mc_rsvd_cc;
+/* 0x0d0 */ u32 mc_emem_arb_da_turns;
+/* 0x0d4 */ u32 mc_emem_arb_da_covers;
+/* 0x0d8 */ u32 mc_emem_arb_misc0;
+/* 0x0dc */ u32 mc_emem_arb_misc1;
+/* 0x0e0 */ u32 mc_emem_arb_ring1_throttle;
+/* 0x0e4 */ u32 mc_emem_arb_ring3_throttle;
+/* 0x0e8 */ u32 mc_emem_arb_override;
+/* 0x0ec */ u32 mc_emem_arb_rsv;
+/* 0x0f0 */ u32 mc_rsvd_f0;
+/* 0x0f4 */ u32 mc_clken_override;
+/* 0x0f8 */ u32 mc_timing_control_dbg;
+/* 0x0fc */ u32 mc_timing_control;
+/* 0x100 */ u32 mc_stat_control;
+/* 0x104 */ u32 mc_stat_status;
+/* 0x108 */ u32 mc_stat_emc_clock_limit;
+/* 0x10c */ u32 mc_stat_emc_clock_limit_msbs;
+/* 0x110 */ u32 mc_stat_emc_clocks;
+/* 0x114 */ u32 mc_stat_emc_clocks_msbs;
+/* 0x118 */ u32 mc_stat_emc_filter_set0_adr_limit_lo;
+/* 0x11c */ u32 mc_stat_emc_filter_set0_adr_limit_hi;
+/* 0x120 */ u32 mc_stat_emc_filter_set0_slack_limit;
+/* 0x124 */ u32 mc_rsvd_124;
+/* 0x128 */ u32 mc_stat_emc_filter_set0_client_0;
+/* 0x12c */ u32 mc_stat_emc_filter_set0_client_1;
+/* 0x130 */ u32 mc_stat_emc_filter_set0_client_2;
+/* 0x134 */ u32 mc_stat_emc_filter_set0_client_3;
+/* 0x138 */ u32 mc_stat_emc_set0_count;
+/* 0x13c */ u32 mc_stat_emc_set0_count_msbs;
+/* 0x140 */ u32 mc_stat_emc_set0_slack_accum;
+/* 0x144 */ u32 mc_stat_emc_set0_slack_accum_msbs;
+/* 0x148 */ u32 mc_stat_emc_set0_histo_count;
+/* 0x14c */ u32 mc_stat_emc_set0_histo_count_msbs;
+/* 0x150 */ u32 mc_stat_emc_set0_minimum_slack_observed;
+/* 0x154 */ u32 mc_rsvd_154;
+/* 0x158 */ u32 mc_stat_emc_filter_set1_adr_limit_lo;
+/* 0x15c */ u32 mc_stat_emc_filter_set1_adr_limit_hi;
+/* 0x160 */ u32 mc_stat_emc_filter_set1_slack_limit;
+/* 0x164 */ u32 mc_rsvd_164;
+/* 0x168 */ u32 mc_stat_emc_filter_set1_client_0;
+/* 0x16c */ u32 mc_stat_emc_filter_set1_client_1;
+/* 0x170 */ u32 mc_stat_emc_filter_set1_client_2;
+/* 0x174 */ u32 mc_stat_emc_filter_set1_client_3;
+/* 0x178 */ u32 mc_stat_emc_set1_count;
+/* 0x17c */ u32 mc_stat_emc_set1_count_msbs;
+/* 0x180 */ u32 mc_stat_emc_set1_slack_accum;
+/* 0x184 */ u32 mc_stat_emc_set1_slack_accum_msbs;
+/* 0x188 */ u32 mc_stat_emc_set1_histo_count;
+/* 0x18c */ u32 mc_stat_emc_set1_histo_count_msbs;
+/* 0x190 */ u32 mc_stat_emc_set1_minimum_slack_observed;
+/* 0x194 */ u32 mc_rsvd_194;
+/* 0x198 */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_lo;
+/* 0x19c */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_hi;
+/* 0x1a0 */ u32 mc_stat_emc_filter_set0_asid;
+/* 0x1a4 */ u32 mc_rsvd_1a4;
+/* 0x1a8 */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_lo;
+/* 0x1ac */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_hi;
+/* 0x1b0 */ u32 mc_stat_emc_filter_set1_asid;
+/* 0x1b4 */ u32 mc_rsvd_1b4;
+/* 0x1b8 */ u32 mc_stat_emc_set0_idle_cycle_count;
+/* 0x1bc */ u32 mc_stat_emc_set0_idle_cycl_count_msbs;
+/* 0x1c0 */ u32 mc_stat_emc_set0_idle_cycle_partition_select;
+/* 0x1c4 */ u32 mc_rsvd_1c4;
+/* 0x1c8 */ u32 mc_stat_emc_set1_idle_cycle_count;
+/* 0x1cc */ u32 mc_stat_emc_set1_idle_cycl_count_msbs;
+/* 0x1d0 */ u32 mc_stat_emc_set1_idle_cycle_partition_select;
+/* 0x1d4 */ u32 mc_rsvd_1d4[6];
+/* 0x1ec */ u32 mc_smmu_stats_tlb_hit_miss_source;
+/* 0x1f0 */ u32 mc_smmu_stats_tlb_hit_count;
+/* 0x1f4 */ u32 mc_smmu_stats_tlb_miss_count;
+/* 0x1f8 */ u32 mc_smmu_stats_ptc_hit_count;
+/* 0x1fc */ u32 mc_smmu_stats_ptc_miss_count;
+/* 0x200 */ u32 mc_client_hotreset_ctrl;
+/* 0x204 */ u32 mc_client_hotreset_status;
+/* 0x208 */ u32 mc_emem_arb_isochronous_0;
+/* 0x20c */ u32 mc_emem_arb_isochronous_1;
+/* 0x210 */ u32 mc_emem_arb_isochronous_2;
+/* 0x214 */ u32 mc_emem_arb_isochronous_3;
+/* 0x218 */ u32 mc_emem_arb_hysteresis_0;
+/* 0x21c */ u32 mc_emem_arb_hysteresis_1;
+/* 0x220 */ u32 mc_emem_arb_hysteresis_2;
+/* 0x224 */ u32 mc_emem_arb_hysteresis_3;
+/* 0x228 */ u32 mc_smmu_translation_enable_0;
+/* 0x22c */ u32 mc_smmu_translation_enable_1;
+/* 0x230 */ u32 mc_smmu_translation_enable_2;
+/* 0x234 */ u32 mc_smmu_translation_enable_3;
+/* 0x238 */ u32 mc_smmu_afi_asid;
+/* 0x23c */ u32 mc_smmu_avpc_asid;
+/* 0x240 */ u32 mc_smmu_dc_asid;
+/* 0x244 */ u32 mc_smmu_dcb_asid;
+/* 0x248 */ u32 mc_rsvd_248[2];
+/* 0x250 */ u32 mc_smmu_hc_asid;
+/* 0x254 */ u32 mc_smmu_hda_asid;
+/* 0x258 */ u32 mc_smmu_isp2_asid;
+/* 0x25c */ u32 mc_rsvd_25c[2];
+/* 0x264 */ u32 mc_smmu_nvenc_asid;
+/* 0x268 */ u32 mc_rsvd_268[2];
+/* 0x270 */ u32 mc_smmu_ppcs_asid;
+/* 0x274 */ u32 mc_smmu_sata_asid;
+/* 0x278 */ u32 mc_rsvd_278[2];
+/* 0x280 */ u32 mc_smmu_vi_asid;
+/* 0x284 */ u32 mc_smmu_vic_asid;
+/* 0x288 */ u32 mc_smmu_xusb_host_asid;
+/* 0x28c */ u32 mc_smmu_xusb_dev_asid;
+/* 0x290 */ u32 mc_smmu_a9avp_asid;
+/* 0x294 */ u32 mc_smmu_tsec_asid;
+/* 0x298 */ u32 mc_smmu_ppcs1_asid;
+/* 0x29c */ u32 mc_rsvd_29c;
+/* 0x2a0 */ u32 mc_ahb_extra_snap_levels;
+/* 0x2a4 */ u32 mc_apb_extra_snap_levels;
+/* 0x2a8 */ u32 mc_avp_extra_snap_levels;
+/* 0x2ac */ u32 mc_dis_extra_snap_levels;
+/* 0x2b0 */ u32 mc_rsvd_2b0[2];
+/* 0x2b8 */ u32 mc_pcx_extra_snap_levels;
+/* 0x2bc */ u32 mc_ftop_extra_snap_levels;
+/* 0x2c0 */ u32 mc_sax_extra_snap_levels;
+/* 0x2c4 */ u32 mc_rsvd_2c4[5];
+/* 0x2d8 */ u32 mc_ve_extra_snap_levels;
+/* 0x2dc */ u32 mc_rsvd_2dc;
+/* 0x2e0 */ u32 mc_latency_allowance_afi_0;
+/* 0x2e4 */ u32 mc_latency_allowance_avpc_0;
+/* 0x2e8 */ u32 mc_latency_allowance_dc_0;
+/* 0x2ec */ u32 mc_latency_allowance_dc_1;
+/* 0x2f0 */ u32 mc_latency_allowance_dc_2;
+/* 0x2f4 */ u32 mc_latency_allowance_dcb_0;
+/* 0x2f8 */ u32 mc_latency_allowance_dcb_1;
+/* 0x2fc */ u32 mc_latency_allowance_dcb_2;
+/* 0x300 */ u32 mc_rsvd_300[4];
+/* 0x310 */ u32 mc_latency_allowance_hc_0;
+/* 0x314 */ u32 mc_latency_allowance_hc_1;
+/* 0x318 */ u32 mc_latency_allowance_hda_0;
+/* 0x31c */ u32 mc_rsvd_31c;
+/* 0x320 */ u32 mc_latency_allowance_mpcore_0;
+/* 0x324 */ u32 mc_rsvd_324;
+/* 0x328 */ u32 mc_latency_allowance_nvenc_0;
+/* 0x32c */ u32 mc_rsvd_32c[6];
+/* 0x344 */ u32 mc_latency_allowance_ppcs_0;
+/* 0x348 */ u32 mc_latency_allowance_ppcs_1;
+/* 0x34c */ u32 mc_latency_allowance_ptc_0;
+/* 0x350 */ u32 mc_latency_allowance_sata_0;
+/* 0x354 */ u32 mc_rsvd_354[7];
+/* 0x370 */ u32 mc_latency_allowance_isp2_0;
+/* 0x374 */ u32 mc_latency_allowance_isp2_1;
+/* 0x378 */ u32 mc_rsvd_378;
+/* 0x37c */ u32 mc_latency_allowance_xusb_0;
+/* 0x380 */ u32 mc_latency_allowance_xusb_1;
+/* 0x384 */ u32 mc_latency_allowance_isp2b_0;
+/* 0x388 */ u32 mc_latency_allowance_isp2b_1;
+/* 0x38c */ u32 mc_rsvd_38c;
+/* 0x390 */ u32 mc_latency_allowance_tsec_0;
+/* 0x394 */ u32 mc_latency_allowance_vic_0;
+/* 0x398 */ u32 mc_latency_allowance_vi2_0;
+/* 0x39c */ u32 mc_rsvd_39c;
+/* 0x3a0 */ u32 mc_latency_allowance_axiap_0;
+/* 0x3a4 */ u32 mc_latency_allowance_a9avp_0;
+/* 0x3a8 */ u32 mc_rsvd_3a8;
+/* 0x3ac */ u32 mc_latency_allowance_gpu_0;
+/* 0x3b0 */ u32 mc_rsvd_3b0[2];
+/* 0x3b8 */ u32 mc_latency_allowance_sdmmca_0;
+/* 0x3bc */ u32 mc_latency_allowance_sdmmcaa_0;
+/* 0x3c0 */ u32 mc_latency_allowance_sdmmc_0;
+/* 0x3c4 */ u32 mc_latency_allowance_sdmmcab_0;
+/* 0x3c8 */ u32 mc_latency_allowance_dc_3;
+/* 0x3cc */ u32 mc_rsvd_3cc[3];
+/* 0x3d8 */ u32 mc_latency_allowance_nvdec_0;
+/* 0x3dc */ u32 mc_latency_allowance_ape_0;
+/* 0x3e0 */ u32 mc_latency_allowance_se_0;
+/* 0x3e4 */ u32 mc_latency_allowance_nvjpg_0;
+/* 0x3e8 */ u32 mc_latency_allowance_gpu2_0;
+/* 0x3ec */ u32 mc_latency_allowance_etr_0;
+/* 0x3f0 */ u32 mc_latency_allowance_tsecb_0;
+/* 0x3f4 */ u32 mc_rsvd_3f4[2];
+/* 0x3fc */ u32 mc_reserved_rsv;
+/* 0x400 */ u32 mc_rsvd_400;
+/* 0x404 */ u32 mc_usbx_extra_snap_levels;
+/* 0x408 */ u32 mc_disb_extra_snap_levels;
+/* 0x40c */ u32 mc_mse_extra_snap_levels;
+/* 0x410 */ u32 mc_ve2_extra_snap_levels;
+/* 0x414 */ u32 mc_a9avppc_extra_snap_levels;
+/* 0x418 */ u32 mc_video_protect_vpr_override;
+/* 0x41c */ u32 mc_dis_ptsa_rate;
+/* 0x420 */ u32 mc_dis_ptsa_min;
+/* 0x424 */ u32 mc_dis_ptsa_max;
+/* 0x428 */ u32 mc_disb_ptsa_rate;
+/* 0x42c */ u32 mc_disb_ptsa_min;
+/* 0x430 */ u32 mc_disb_ptsa_max;
+/* 0x434 */ u32 mc_ve_ptsa_rate;
+/* 0x438 */ u32 mc_ve_ptsa_min;
+/* 0x43c */ u32 mc_ve_ptsa_max;
+/* 0x440 */ u32 mc_ring2_ptsa_rate;
+/* 0x444 */ u32 mc_ring2_ptsa_min;
+/* 0x448 */ u32 mc_ring2_ptsa_max;
+/* 0x44c */ u32 mc_mll_mpcorer_ptsa_rate;
+/* 0x450 */ u32 mc_mll_mpcorer_ptsa_min;
+/* 0x454 */ u32 mc_mll_mpcorer_ptsa_max;
+/* 0x458 */ u32 mc_smmu_smmu_ptsa_rate;
+/* 0x45c */ u32 mc_smmu_smmu_ptsa_min;
+/* 0x460 */ u32 mc_smmu_smmu_ptsa_max;
+/* 0x464 */ u32 mc_rsvd_464[6];
+/* 0x47c */ u32 mc_ring1_ptsa_rate;
+/* 0x480 */ u32 mc_ring1_ptsa_min;
+/* 0x484 */ u32 mc_ring1_ptsa_max;
+/* 0x488 */ u32 mc_a9avppc_ptsa_rate;
+/* 0x48c */ u32 mc_a9avppc_ptsa_min;
+/* 0x490 */ u32 mc_a9avppc_ptsa_max;
+/* 0x494 */ u32 mc_ve2_ptsa_rate;
+/* 0x498 */ u32 mc_ve2_ptsa_min;
+/* 0x49c */ u32 mc_ve2_ptsa_max;
+/* 0x4a0 */ u32 mc_isp_ptsa_rate;
+/* 0x4a4 */ u32 mc_isp_ptsa_min;
+/* 0x4a8 */ u32 mc_isp_ptsa_max;
+/* 0x4ac */ u32 mc_pcx_ptsa_rate;
+/* 0x4b0 */ u32 mc_pcx_ptsa_min;
+/* 0x4b4 */ u32 mc_pcx_ptsa_max;
+/* 0x4b8 */ u32 mc_sax_ptsa_rate;
+/* 0x4bc */ u32 mc_sax_ptsa_min;
+/* 0x4c0 */ u32 mc_sax_ptsa_max;
+/* 0x4c4 */ u32 mc_mse_ptsa_rate;
+/* 0x4c8 */ u32 mc_mse_ptsa_min;
+/* 0x4cc */ u32 mc_mse_ptsa_max;
+/* 0x4d0 */ u32 mc_sd_ptsa_rate;
+/* 0x4d4 */ u32 mc_sd_ptsa_min;
+/* 0x4d8 */ u32 mc_sd_ptsa_max;
+/* 0x4dc */ u32 mc_ahb_ptsa_rate;
+/* 0x4e0 */ u32 mc_ahb_ptsa_min;
+/* 0x4e4 */ u32 mc_ahb_ptsa_max;
+/* 0x4e8 */ u32 mc_apb_ptsa_rate;
+/* 0x4ec */ u32 mc_apb_ptsa_min;
+/* 0x4f0 */ u32 mc_apb_ptsa_max;
+/* 0x4f4 */ u32 mc_avp_ptsa_rate;
+/* 0x4f8 */ u32 mc_avp_ptsa_min;
+/* 0x4fc */ u32 mc_avp_ptsa_max;
+/* 0x500 */ u32 mc_rsvd_500[3];
+/* 0x50c */ u32 mc_ftop_ptsa_rate;
+/* 0x510 */ u32 mc_ftop_ptsa_min;
+/* 0x514 */ u32 mc_ftop_ptsa_max;
+/* 0x518 */ u32 mc_host_ptsa_rate;
+/* 0x51c */ u32 mc_host_ptsa_min;
+/* 0x520 */ u32 mc_host_ptsa_max;
+/* 0x524 */ u32 mc_usbx_ptsa_rate;
+/* 0x528 */ u32 mc_usbx_ptsa_min;
+/* 0x52c */ u32 mc_usbx_ptsa_max;
+/* 0x530 */ u32 mc_usbd_ptsa_rate;
+/* 0x534 */ u32 mc_usbd_ptsa_min;
+/* 0x538 */ u32 mc_usbd_ptsa_max;
+/* 0x53c */ u32 mc_gk_ptsa_rate;
+/* 0x540 */ u32 mc_gk_ptsa_min;
+/* 0x544 */ u32 mc_gk_ptsa_max;
+/* 0x548 */ u32 mc_aud_ptsa_rate;
+/* 0x54c */ u32 mc_aud_ptsa_min;
+/* 0x550 */ u32 mc_aud_ptsa_max;
+/* 0x554 */ u32 mc_vicpc_ptsa_rate;
+/* 0x558 */ u32 mc_vicpc_ptsa_min;
+/* 0x55c */ u32 mc_vicpc_ptsa_max;
+/* 0x560 */ u32 mc_rsvd_560[9];
+/* 0x584 */ u32 mc_jpg_ptsa_rate;
+/* 0x588 */ u32 mc_jpg_ptsa_min;
+/* 0x58c */ u32 mc_jpg_ptsa_max;
+/* 0x590 */ u32 mc_video_protect_vpr_override1;
+/* 0x594 */ u32 mc_rsvd_594[27];
+/* 0x600 */ u32 mc_smmu_tlb_set_selection_mask_0;
+/* 0x604 */ u32 mc_rsvd_604[3];
+/* 0x610 */ u32 mc_gk2_ptsa_rate;
+/* 0x614 */ u32 mc_gk2_ptsa_min;
+/* 0x618 */ u32 mc_gk2_ptsa_max;
+/* 0x61c */ u32 mc_sdm_ptsa_rate;
+/* 0x620 */ u32 mc_sdm_ptsa_min;
+/* 0x624 */ u32 mc_sdm_ptsa_max;
+/* 0x628 */ u32 mc_hdapc_ptsa_rate;
+/* 0x62c */ u32 mc_hdapc_ptsa_min;
+/* 0x630 */ u32 mc_hdapc_ptsa_max;
+/* 0x634 */ u32 mc_dfd_ptsa_rate;
+/* 0x638 */ u32 mc_dfd_ptsa_min;
+/* 0x63c */ u32 mc_dfd_ptsa_max;
+/* 0x640 */ u32 mc_rsvd_640[2];
+/* 0x648 */ u32 mc_video_protect_bom;
+/* 0x64c */ u32 mc_video_protect_size_mb;
+/* 0x650 */ u32 mc_video_protect_reg_ctrl;
+/* 0x654 */ u32 mc_err_vpr_status;
+/* 0x658 */ u32 mc_err_vpr_adr;
+/* 0x65c */ u32 mc_iram_bom;
+/* 0x660 */ u32 mc_iram_tom;
+/* 0x664 */ u32 mc_emem_cfg_access_ctrl;
+/* 0x668 */ u32 mc_tz_security_ctrl;
+/* 0x66c */ u32 mc_emem_arb_outstanding_req_ring3;
+/* 0x670 */ u32 mc_sec_carveout_bom;
+/* 0x674 */ u32 mc_sec_carveout_size_mb;
+/* 0x678 */ u32 mc_sec_carveout_reg_ctrl;
+/* 0x67c */ u32 mc_err_sec_status;
+/* 0x680 */ u32 mc_err_sec_adr;
+/* 0x684 */ u32 mc_pc_idle_clock_gate_config;
+/* 0x688 */ u32 mc_stutter_control;
+/* 0x68c */ u32 mc_rsvd_68c;
+/* 0x690 */ u32 mc_scaled_latency_allowance_display0a;
+/* 0x694 */ u32 mc_scaled_latency_allowance_display0ab;
+/* 0x698 */ u32 mc_scaled_latency_allowance_display0b;
+/* 0x69c */ u32 mc_scaled_latency_allowance_display0bb;
+/* 0x6a0 */ u32 mc_scaled_latency_allowance_display0c;
+/* 0x6a4 */ u32 mc_scaled_latency_allowance_display0cb;
+/* 0x6a8 */ u32 mc_rsvd_6a8[2];
+/* 0x6b0 */ u32 mc_emem_arb_niso_throttle;
+/* 0x6b4 */ u32 mc_emem_arb_outstanding_req_niso;
+/* 0x6b8 */ u32 mc_emem_arb_niso_throttle_mask;
+/* 0x6bc */ u32 mc_emem_arb_ring0_throttle_mask;
+/* 0x6c0 */ u32 mc_emem_arb_timing_rfcpb;
+/* 0x6c4 */ u32 mc_emem_arb_timing_ccdmw;
+/* 0x6c8 */ u32 mc_rsvd_6c8[10];
+/* 0x6f0 */ u32 mc_emem_arb_refpb_hp_ctrl;
+/* 0x6f4 */ u32 mc_emem_arb_refpb_bank_ctrl;
+/* 0x6f8 */ u32 mc_rsvd_6f8[67];
+/* 0x804 */ u32 mc_smmu_isp21_asid_b01;
+/* 0x808 */ u32 mc_smmu_isp2b1_asid_b01;
+/* 0x80c */ u32 mc_rsvd_80c[32];
+/* 0x88c */ u32 mc_min_length_afi_0;
+/* 0x890 */ u32 mc_min_length_avpc_0;
+/* 0x894 */ u32 mc_min_length_dc_0;
+/* 0x898 */ u32 mc_min_length_dc_1;
+/* 0x89c */ u32 mc_min_length_dc_2;
+/* 0x8a0 */ u32 mc_min_length_dcb_0;
+/* 0x8a4 */ u32 mc_min_length_dcb_1;
+/* 0x8a8 */ u32 mc_min_length_dcb_2;
+/* 0x8ac */ u32 mc_rsvd_8ac[4];
+/* 0x8bc */ u32 mc_min_length_hc_0;
+/* 0x8c0 */ u32 mc_min_length_hc_1;
+/* 0x8c4 */ u32 mc_min_length_hda_0;
+/* 0x8c8 */ u32 mc_rsvd_8c8;
+/* 0x8cc */ u32 mc_min_length_mpcore_0;
+/* 0x8d0 */ u32 mc_rsvd_8d0;
+/* 0x8d4 */ u32 mc_min_length_nvenc_0;
+/* 0x8d8 */ u32 mc_rsvd_8d8[6];
+/* 0x8f0 */ u32 mc_min_length_ppcs_0;
+/* 0x8f4 */ u32 mc_min_length_ppcs_1;
+/* 0x8f8 */ u32 mc_min_length_ptc_0;
+/* 0x8fc */ u32 mc_min_length_sata_0;
+/* 0x900 */ u32 mc_rsvd_900[7];
+/* 0x91c */ u32 mc_min_length_isp2_0;
+/* 0x920 */ u32 mc_min_length_isp2_1;
+/* 0x924 */ u32 mc_rsvd_924;
+/* 0x928 */ u32 mc_min_length_xusb_0;
+/* 0x92c */ u32 mc_min_length_xusb_1;
+/* 0x930 */ u32 mc_min_length_isp2b_0;
+/* 0x934 */ u32 mc_min_length_isp2b_1;
+/* 0x938 */ u32 mc_rsvd_938;
+/* 0x93c */ u32 mc_min_length_tsec_0;
+/* 0x940 */ u32 mc_min_length_vic_0;
+/* 0x944 */ u32 mc_min_length_vi2_0;
+/* 0x948 */ u32 mc_untranslated_region_check_b01;
+/* 0x94c */ u32 mc_min_length_axiap_0;
+/* 0x950 */ u32 mc_min_length_a9avp_0;
+/* 0x954 */ u32 mc_rsvd_954;
+/* 0x958 */ u32 mc_reserved_rsv_1;
+/* 0x95c */ u32 mc_dvfs_pipe_select;
+/* 0x960 */ u32 mc_ptsa_grant_decrement;
+/* 0x964 */ u32 mc_iram_reg_ctrl;
+/* 0x968 */ u32 mc_emem_arb_override_1;
+/* 0x96c */ u32 mc_rsvd_96c;
+/* 0x970 */ u32 mc_client_hotreset_ctrl_1;
+/* 0x974 */ u32 mc_client_hotreset_status_1;
+/* 0x978 */ u32 mc_video_protect_bom_adr_hi;
+/* 0x97c */ u32 mc_rsvd_97c;
+/* 0x980 */ u32 mc_iram_adr_hi;
+/* 0x984 */ u32 mc_video_protect_gpu_override_0;
+/* 0x988 */ u32 mc_video_protect_gpu_override_1;
+/* 0x98c */ u32 mc_rsvd_98c;
+/* 0x990 */ u32 mc_emem_arb_stats_0;
+/* 0x994 */ u32 mc_emem_arb_stats_1;
+/* 0x998 */ u32 mc_rsvd_998[2];
+/* 0x9a0 */ u32 mc_mts_carveout_bom;
+/* 0x9a4 */ u32 mc_mts_carveout_size_mb;
+/* 0x9a8 */ u32 mc_mts_carveout_adr_hi;
+/* 0x9ac */ u32 mc_mts_carveout_reg_ctrl;
+/* 0x9b0 */ u32 mc_err_mts_status;
+/* 0x9b4 */ u32 mc_err_mts_adr;
+/* 0x9b8 */ u32 mc_smmu_ptc_flush_1;
+/* 0x9bc */ u32 mc_security_cfg3;
+/* 0x9c0 */ u32 mc_rsvd_9c0[4];
+/* 0x9d0 */ u32 mc_err_apb_asid_update_status;
+/* 0x9d4 */ u32 mc_sec_carveout_adr_hi;
+/* 0x9d8 */ u32 mc_rsvd_9d8;
+/* 0x9dc */ u32 mc_da_config0;
+/* 0x9e0 */ u32 mc_smmu_asid_security_2;
+/* 0x9e4 */ u32 mc_smmu_asid_security_3;
+/* 0x9e8 */ u32 mc_smmu_asid_security_4;
+/* 0x9ec */ u32 mc_smmu_asid_security_5;
+/* 0x9f0 */ u32 mc_smmu_asid_security_6;
+/* 0x9f4 */ u32 mc_smmu_asid_security_7;
+/* 0x9f8 */ u32 mc_rsvd_9f8[2];
+/* 0xa00 */ u32 mc_gk_extra_snap_levels;
+/* 0xa04 */ u32 mc_sd_extra_snap_levels;
+/* 0xa08 */ u32 mc_isp_extra_snap_levels;
+/* 0xa0c */ u32 mc_rsvd_a0c;
+/* 0xa10 */ u32 mc_aud_extra_snap_levels;
+/* 0xa14 */ u32 mc_host_extra_snap_levels;
+/* 0xa18 */ u32 mc_usbd_extra_snap_levels;
+/* 0xa1c */ u32 mc_vicpc_extra_snap_levels;
+/* 0xa20 */ u32 mc_stat_emc_filter_set0_adr_limit_upper;
+/* 0xa24 */ u32 mc_stat_emc_filter_set1_adr_limit_upper;
+/* 0xa28 */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_upper;
+/* 0xa2c */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_upper;
+/* 0xa30 */ u32 mc_rsvd_a30[3];
+/* 0xa3c */ u32 mc_jpg_extra_snap_levels;
+/* 0xa40 */ u32 mc_gk2_extra_snap_levels;
+/* 0xa44 */ u32 mc_sdm_extra_snap_levels;
+/* 0xa48 */ u32 mc_hdapc_extra_snap_levels;
+/* 0xa4c */ u32 mc_dfd_extra_snap_levels;
+/* 0xa50 */ u32 mc_rsvd_a50[14];
+/* 0xa88 */ u32 mc_smmu_dc1_asid;
+/* 0xa8c */ u32 mc_rsvd_a8c[2];
+/* 0xa94 */ u32 mc_smmu_sdmmc1a_asid;
+/* 0xa98 */ u32 mc_smmu_sdmmc2a_asid;
+/* 0xa9c */ u32 mc_smmu_sdmmc3a_asid;
+/* 0xaa0 */ u32 mc_smmu_sdmmc4a_asid;
+/* 0xaa4 */ u32 mc_smmu_isp2b_asid;
+/* 0xaa8 */ u32 mc_smmu_gpu_asid;
+/* 0xaac */ u32 mc_smmu_gpub_asid;
+/* 0xab0 */ u32 mc_smmu_ppcs2_asid;
+/* 0xab4 */ u32 mc_smmu_nvdec_asid;
+/* 0xab8 */ u32 mc_smmu_ape_asid;
+/* 0xabc */ u32 mc_smmu_se_asid;
+/* 0xac0 */ u32 mc_smmu_nvjpg_asid;
+/* 0xac4 */ u32 mc_smmu_hc1_asid;
+/* 0xac8 */ u32 mc_smmu_se1_asid;
+/* 0xacc */ u32 mc_smmu_axiap_asid;
+/* 0xad0 */ u32 mc_smmu_etr_asid;
+/* 0xad4 */ u32 mc_smmu_tsecb_asid;
+/* 0xad8 */ u32 mc_smmu_tsec1_asid;
+/* 0xadc */ u32 mc_smmu_tsecb1_asid;
+/* 0xae0 */ u32 mc_smmu_nvdec1_asid;
+/* 0xae4 */ u32 mc_rsvd_ae4[8];
+/* 0xb04 */ u32 mc_min_length_gpu_0;
+/* 0xb08 */ u32 mc_rsvd_b08[2];
+/* 0xb10 */ u32 mc_min_length_sdmmca_0;
+/* 0xb14 */ u32 mc_min_length_sdmmcaa_0;
+/* 0xb18 */ u32 mc_min_length_sdmmc_0;
+/* 0xb1c */ u32 mc_min_length_sdmmcab_0;
+/* 0xb20 */ u32 mc_min_length_dc_3;
+/* 0xb24 */ u32 mc_rsvd_b24[3];
+/* 0xb30 */ u32 mc_min_length_nvdec_0;
+/* 0xb34 */ u32 mc_min_length_ape_0;
+/* 0xb38 */ u32 mc_min_length_se_0;
+/* 0xb3c */ u32 mc_min_length_nvjpg_0;
+/* 0xb40 */ u32 mc_min_length_gpu2_0;
+/* 0xb44 */ u32 mc_min_length_etr_0;
+/* 0xb48 */ u32 mc_min_length_tsecb_0;
+/* 0xb4c */ u32 mc_rsvd_b4c[13];
+/* 0xb80 */ u32 mc_emem_arb_niso_throttle_mask_1;
+/* 0xb84 */ u32 mc_emem_arb_hysteresis_4;
+/* 0xb88 */ u32 mc_stat_emc_filter_set0_client_4;
+/* 0xb8c */ u32 mc_stat_emc_filter_set1_client_4;
+/* 0xb90 */ u32 mc_rsvd_b90;
+/* 0xb94 */ u32 mc_emem_arb_isochronous_4;
+/* 0xb98 */ u32 mc_smmu_translation_enable_4;
+/* 0xb9c */ u32 mc_smmu_client_config4;
+/* 0xba0 */ u32 mc_rsvd_ba0[4];
+/* 0xbb0 */ u32 mc_emem_arb_dhysteresis_0;
+/* 0xbb4 */ u32 mc_emem_arb_dhysteresis_1;
+/* 0xbb8 */ u32 mc_emem_arb_dhysteresis_2;
+/* 0xbbc */ u32 mc_emem_arb_dhysteresis_3;
+/* 0xbc0 */ u32 mc_emem_arb_dhysteresis_4;
+/* 0xbc4 */ u32 mc_rsvd_bc4[2];
+/* 0xbcc */ u32 mc_emem_arb_dhyst_ctrl;
+/* 0xbd0 */ u32 mc_emem_arb_dhyst_timeout_util_0;
+/* 0xbd4 */ u32 mc_emem_arb_dhyst_timeout_util_1;
+/* 0xbd8 */ u32 mc_emem_arb_dhyst_timeout_util_2;
+/* 0xbdc */ u32 mc_emem_arb_dhyst_timeout_util_3;
+/* 0xbe0 */ u32 mc_emem_arb_dhyst_timeout_util_4;
+/* 0xbe4 */ u32 mc_emem_arb_dhyst_timeout_util_5;
+/* 0xbe8 */ u32 mc_emem_arb_dhyst_timeout_util_6;
+/* 0xbec */ u32 mc_emem_arb_dhyst_timeout_util_7;
+/* 0xbf0 */ u32 mc_rsvd_bf0[4];
+/* 0xc00 */ u32 mc_err_generalized_carveout_status;
+/* 0xc04 */ u32 mc_err_generalized_carveout_adr;
+/* 0xc08 */ u32 mc_security_carveout1_cfg0;
+/* 0xc0c */ u32 mc_security_carveout1_bom;
+/* 0xc10 */ u32 mc_security_carveout1_bom_hi;
+/* 0xc14 */ u32 mc_security_carveout1_size_128kb;
+/* 0xc18 */ u32 mc_security_carveout1_client_access0;
+/* 0xc1c */ u32 mc_security_carveout1_client_access1;
+/* 0xc20 */ u32 mc_security_carveout1_client_access2;
+/* 0xc24 */ u32 mc_security_carveout1_client_access3;
+/* 0xc28 */ u32 mc_security_carveout1_client_access4;
+/* 0xc2c */ u32 mc_security_carveout1_client_force_internal_access0;
+/* 0xc30 */ u32 mc_security_carveout1_client_force_internal_access1;
+/* 0xc34 */ u32 mc_security_carveout1_client_force_internal_access2;
+/* 0xc38 */ u32 mc_security_carveout1_client_force_internal_access3;
+/* 0xc3c */ u32 mc_security_carveout1_client_force_internal_access4;
+/* 0xc40 */ u32 mc_rsvd_c40[6];
+/* 0xc58 */ u32 mc_security_carveout2_cfg0;
+/* 0xc5c */ u32 mc_security_carveout2_bom;
+/* 0xc60 */ u32 mc_security_carveout2_bom_hi;
+/* 0xc64 */ u32 mc_security_carveout2_size_128kb;
+/* 0xc68 */ u32 mc_security_carveout2_client_access0;
+/* 0xc6c */ u32 mc_security_carveout2_client_access1;
+/* 0xc70 */ u32 mc_security_carveout2_client_access2;
+/* 0xc74 */ u32 mc_security_carveout2_client_access3;
+/* 0xc78 */ u32 mc_security_carveout2_client_access4;
+/* 0xc7c */ u32 mc_security_carveout2_client_force_internal_access0;
+/* 0xc80 */ u32 mc_security_carveout2_client_force_internal_access1;
+/* 0xc84 */ u32 mc_security_carveout2_client_force_internal_access2;
+/* 0xc88 */ u32 mc_security_carveout2_client_force_internal_access3;
+/* 0xc8c */ u32 mc_security_carveout2_client_force_internal_access4;
+/* 0xc90 */ u32 mc_rsvd_c90[6];
+/* 0xca8 */ u32 mc_security_carveout3_cfg0;
+/* 0xcac */ u32 mc_security_carveout3_bom;
+/* 0xcb0 */ u32 mc_security_carveout3_bom_hi;
+/* 0xcb4 */ u32 mc_security_carveout3_size_128kb;
+/* 0xcb8 */ u32 mc_security_carveout3_client_access0;
+/* 0xcbc */ u32 mc_security_carveout3_client_access1;
+/* 0xcc0 */ u32 mc_security_carveout3_client_access2;
+/* 0xcc4 */ u32 mc_security_carveout3_client_access3;
+/* 0xcc8 */ u32 mc_security_carveout3_client_access4;
+/* 0xccc */ u32 mc_security_carveout3_client_force_internal_access0;
+/* 0xcd0 */ u32 mc_security_carveout3_client_force_internal_access1;
+/* 0xcd4 */ u32 mc_security_carveout3_client_force_internal_access2;
+/* 0xcd8 */ u32 mc_security_carveout3_client_force_internal_access3;
+/* 0xcdc */ u32 mc_security_carveout3_client_force_internal_access4;
+/* 0xce0 */ u32 mc_rsvd_ce0[6];
+/* 0xcf8 */ u32 mc_security_carveout4_cfg0;
+/* 0xcfc */ u32 mc_security_carveout4_bom;
+/* 0xd00 */ u32 mc_security_carveout4_bom_hi;
+/* 0xd04 */ u32 mc_security_carveout4_size_128kb;
+/* 0xd08 */ u32 mc_security_carveout4_client_access0;
+/* 0xd0c */ u32 mc_security_carveout4_client_access1;
+/* 0xd10 */ u32 mc_security_carveout4_client_access2;
+/* 0xd14 */ u32 mc_security_carveout4_client_access3;
+/* 0xd18 */ u32 mc_security_carveout4_client_access4;
+/* 0xd1c */ u32 mc_security_carveout4_client_force_internal_access0;
+/* 0xd20 */ u32 mc_security_carveout4_client_force_internal_access1;
+/* 0xd24 */ u32 mc_security_carveout4_client_force_internal_access2;
+/* 0xd28 */ u32 mc_security_carveout4_client_force_internal_access3;
+/* 0xd2c */ u32 mc_security_carveout4_client_force_internal_access4;
+/* 0xd30 */ u32 mc_rsvd_d30[6];
+/* 0xd48 */ u32 mc_security_carveout5_cfg0;
+/* 0xd4c */ u32 mc_security_carveout5_bom;
+/* 0xd50 */ u32 mc_security_carveout5_bom_hi;
+/* 0xd54 */ u32 mc_security_carveout5_size_128kb;
+/* 0xd58 */ u32 mc_security_carveout5_client_access0;
+/* 0xd5c */ u32 mc_security_carveout5_client_access1;
+/* 0xd60 */ u32 mc_security_carveout5_client_access2;
+/* 0xd64 */ u32 mc_security_carveout5_client_access3;
+/* 0xd68 */ u32 mc_security_carveout5_client_access4;
+/* 0xd6c */ u32 mc_security_carveout5_client_force_internal_access0;
+/* 0xd70 */ u32 mc_security_carveout5_client_force_internal_access1;
+/* 0xd74 */ u32 mc_security_carveout5_client_force_internal_access2;
+/* 0xd78 */ u32 mc_security_carveout5_client_force_internal_access3;
+/* 0xd7c */ u32 mc_security_carveout5_client_force_internal_access4;
+/* 0xd80 */ u32 mc_rsvd_d80[20];
+/* 0xdd0 */ u32 mc_pcfifo_client_config0;
+/* 0xdd4 */ u32 mc_pcfifo_client_config1;
+/* 0xdd8 */ u32 mc_pcfifo_client_config2;
+/* 0xddc */ u32 mc_pcfifo_client_config3;
+/* 0xde0 */ u32 mc_pcfifo_client_config4;
+} mc_regs_t210_t;
+
#endif