OmniNX/hekate
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bdk: se: adjust T210 silicon errata coherency WAR

Browse Source 
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
This commit is contained in:
CTCaer
2026-01-15 19:02:36 +02:00
parent e3267d1db7
commit 68281d3051
1 changed files with 20 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
bdk/sec/se.c
View File

@@ -91,28 +91,33 @@ static int _se_op_wait()
return 0; return 0;
} }
// T210B01: IRAM/TZRAM/DRAM AHB coherency WAR. // WAR: Coherency flushing.
if (!tegra_t210 && ll_dst_ptr) if (ll_dst_ptr)
{ {
u32 timeout = get_tmr_us() + 1000000;
// Ensure data is out from SE. // Ensure data is out from SE.
while (SE(SE_STATUS_REG) & SE_STATUS_MEM_IF_BUSY) if (tegra_t210)
usleep(15); // Worst case scenario.
else
{ {
if (get_tmr_us() > timeout) // T210B01 has a status bit for that.
return 0; u32 retries = 500000;
usleep(1); while (SE(SE_STATUS_REG) & SE_STATUS_MEM_IF_BUSY)
{
if (!retries)
return 0;
usleep(1);
retries--;
}
} }
// Ensure data is out from AHB. // Ensure data is out from AHB.
if (ll_dst_ptr->addr >= DRAM_START) u32 retries = 500000;
while (AHB_GIZMO(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID) & MEM_WRQUE_SE_MST_ID)
{ {
timeout = get_tmr_us() + 200000; if (!retries)
while (AHB_GIZMO(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID) & MEM_WRQUE_SE_MST_ID) return 0;
{ usleep(1);
if (get_tmr_us() > timeout) retries--;
return 0;
usleep(1);
}
} }
} }