OmniNX/hekate
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bdk: minerva: remove dependency to Nyx storage

Browse Source 
minerva_str_t must be used now and passed directly to minerva_init.
This commit is contained in:
CTCaer
2025-11-27 11:20:19 +02:00
parent fc71e405d2
commit 62163f3255
3 changed files with 79 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
bdk/mem/minerva.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2024 CTCaer
* Copyright (c) 2019-2025 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -25,23 +25,19 @@
#include <soc/fuse.h>
#include <soc/hw_init.h>
#include <soc/t210.h>
#include <utils/util.h>
#define TABLE_FREQ_KHZ_OFFSET 0x40
#define TABLE_LA_REGS_T210_OFFSET 0x1284
#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4
#define LA_SDMMC1_INDEX 6
extern volatile nyx_storage_t *nyx_str;
static mtc_config_t *mtc_cfg = NULL;
void (*mtc_call)(mtc_config_t *mtc_cfg, void *);
void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
u32 minerva_init()
u32 minerva_init(minerva_str_t *mtc_str)
{
u32 tbl_idx = 0;
minerva_cfg = NULL;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
mtc_call = NULL;
mtc_cfg = (mtc_config_t *)&mtc_str->mtc_cfg;
//!TODO: Not supported on T210B01 yet.
if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
@@ -49,16 +45,16 @@ u32 minerva_init()
#ifdef BDK_MINERVA_CFG_FROM_RAM
// Set table to nyx storage.
mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
mtc_cfg->mtc_table = (emc_table_t *)mtc_str->mtc_table;
// Check if Minerva is already initialized.
if (mtc_cfg->init_done == MTC_INIT_MAGIC)
{
mtc_cfg->train_mode = OP_PERIODIC_TRAIN; // Retrain if needed.
u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
minerva_cfg = (void *)ep_addr;
mtc_call = (void *)ep_addr;
return !minerva_cfg ? 1 : 0;
return !mtc_call ? 1 : 0;
}
else
{
@@ -72,19 +68,19 @@ u32 minerva_init()
// Ensure that Minerva is new.
if (mtc_tmp.init_done == MTC_INIT_MAGIC)
minerva_cfg = (void *)ep_addr;
mtc_call = (void *)ep_addr;
else
mtc_cfg->init_done = 0;
// Copy Minerva context to Nyx storage.
if (minerva_cfg)
if (mtc_call)
memcpy(mtc_cfg, (void *)&mtc_tmp, sizeof(mtc_config_t));
}
#else
memset(mtc_cfg, 0, sizeof(mtc_config_t));
// Set table to nyx storage.
mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
mtc_cfg->mtc_table = (emc_table_t *)mtc_str->mtc_table;
mtc_cfg->sdram_id = fuse_read_dramid(false);
mtc_cfg->init_done = MTC_NEW_MAGIC; // Initialize mtc table.
@@ -93,16 +89,17 @@ u32 minerva_init()
// Ensure that Minerva is new.
if (mtc_cfg->init_done == MTC_INIT_MAGIC)
minerva_cfg = (void *)ep_addr;
mtc_call = (void *)ep_addr;
else
mtc_cfg->init_done = 0;
#endif
if (!minerva_cfg)
if (!mtc_call)
return 1;
// Get current frequency
u32 current_emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC);
u32 tbl_idx = 0;
for (tbl_idx = 0; tbl_idx < mtc_cfg->table_entries; tbl_idx++)
{
if (current_emc_clk_src == mtc_cfg->mtc_table[tbl_idx].clk_src_emc)
@@ -112,36 +109,35 @@ u32 minerva_init()
mtc_cfg->rate_from = mtc_cfg->mtc_table[tbl_idx].rate_khz;
mtc_cfg->rate_to = FREQ_204;
mtc_cfg->train_mode = OP_TRAIN;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
mtc_cfg->rate_to = FREQ_800;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
mtc_cfg->rate_to = FREQ_1600;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
// FSP WAR.
mtc_cfg->train_mode = OP_SWITCH;
mtc_cfg->rate_to = FREQ_800;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
// Switch to max.
mtc_cfg->rate_to = FREQ_1600;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
return 0;
}
void minerva_change_freq(minerva_freq_t freq)
{
if (!minerva_cfg)
if (!mtc_call)
return;
// Check if requested frequency is different. Do not allow otherwise because it will hang.
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
if (mtc_cfg->rate_from != freq)
{
mtc_cfg->rate_to = freq;
mtc_cfg->train_mode = OP_SWITCH;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
}
}
@@ -167,11 +163,9 @@ void minerva_sdmmc_la_program(void *table, bool t210b01)
void minerva_prep_boot_freq()
{
if (!minerva_cfg)
if (!mtc_call)
return;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
// Check if there's RAM OC. If not exit.
if (mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
return;
@@ -184,11 +178,9 @@ void minerva_prep_boot_freq()
void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom, bool prg_sdmmc_la)
{
if (!minerva_cfg)
if (!mtc_call)
return;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
// Program SDMMC LA regs.
if (prg_sdmmc_la)
for (u32 i = 0; i < mtc_cfg->table_entries; i++)
@@ -236,7 +228,7 @@ void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom, bool prg_sdmmc_la)
// Train frequency.
mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
}
// Do FSP WAR and scale to 800 MHz as boot freq.
@@ -251,31 +243,28 @@ void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom, bool prg_sdmmc_la)
void minerva_periodic_training()
{
if (!minerva_cfg)
if (!mtc_call)
return;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
if (mtc_cfg->rate_from == FREQ_1600)
{
mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
minerva_cfg(mtc_cfg, NULL);
mtc_call(mtc_cfg, NULL);
}
}
emc_table_t *minerva_get_mtc_table()
{
if (!minerva_cfg)
if (!mtc_call)
return NULL;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
return mtc_cfg->mtc_table;
}
int minerva_get_mtc_table_entries()
{
if (!minerva_cfg)
if (!mtc_call)
return 0;
mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
return mtc_cfg->table_entries;
}