bdk: make use of new MC/EMC defines
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15
bdk/mem/mc.c
15
bdk/mem/mc.c
@@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2024 CTCaer
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* Copyright (c) 2018-2025 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -21,6 +21,8 @@
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#include <soc/t210.h>
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#include <soc/clock.h>
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#define HOS_WPR1_BASE 0x80020000
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void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock)
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{
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MC(MC_SEC_CARVEOUT_BOM) = bom;
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@@ -32,8 +34,10 @@ void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock)
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void mc_config_carveout()
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{
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// Enable ACR GSR3.
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*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
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*(u32 *)(HOS_WPR1_BASE + SZ_256K - sizeof(u32)) = ACR_GSC3_ENABLE_MAGIC;
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// Set VPR CYA TRUSTED DEFAULT.
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = VPR_OVR0_CYA_TRUST_DEFAULT;
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
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MC(MC_VIDEO_PROTECT_BOM) = 0;
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MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED;
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@@ -77,7 +81,7 @@ void mc_config_carveout()
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// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
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void mc_enable_ahb_redirect()
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{
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// Enable ARC_CLK_OVR_ON.
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// Bypass ARC clock gating.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
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//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
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MC(MC_IRAM_BOM) = IRAM_BASE;
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@@ -90,7 +94,7 @@ void mc_disable_ahb_redirect()
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MC(MC_IRAM_TOM) = 0;
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// Disable IRAM_CFG_WRITE_ACCESS (sticky).
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//MC(MC_IRAM_REG_CTRL) |= BIT(0);
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// Disable ARC_CLK_OVR_ON.
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// Set ARC clock gating to automatic.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= ~BIT(19);
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}
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@@ -110,6 +114,7 @@ void mc_enable()
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{
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// Reset EMC source to PLLP.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u);
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// Enable and clear reset for memory clocks.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
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