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bdk: display: reduce display off waiting time

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And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
This commit is contained in:
CTCaer
2026-01-20 06:13:02 +02:00
parent 28ebdc213e
commit 3134af6e92
2 changed files with 9 additions and 11 deletions
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4
bdk/display/di.c
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@@ -694,8 +694,8 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
DSI(DSI_WR_DATA) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE;
// Wait for 5 frames (HOST1X_CH0_SYNC_SYNCPT_9).
// Not here. Wait for 1 frame manually.
usleep(20000);
// Not here. Wait for 1 frame + transmission manually.
usleep((_panel_id == PANEL_SAM_AMS699VC01) ? (15933 + 195) : (16666 + 230));
// Propagate changes to all register buffers and disable host cmd packets during video.
DISPLAY_A(DC_CMD_STATE_ACCESS) = READ_MUX_ACTIVE | WRITE_MUX_ACTIVE;

16
bdk/soc/hw_init.c
View File

@@ -470,7 +470,12 @@ void hw_init()
void hw_deinit(bool keep_display)
{
bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
// Seamless display or display power off.
if (!keep_display)
{
display_end();
clock_disable_host1x();
}
// Scale down BPMP clock.
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
@@ -495,16 +500,9 @@ void hw_deinit(bool keep_display)
hw_config_arbiter(true);
// Re-enable clocks to Audio Processing Engine as a workaround to rerunning mbist war.
if (tegra_t210)
if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
{
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_AHUB);
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_APE);
}
// Seamless display or display power off.
if (!keep_display)
{
display_end();
clock_disable_host1x();
}
}