From 1fbecfc76aa8f47da907ebfc08d22d436f436860 Mon Sep 17 00:00:00 2001 From: CTCaer Date: Sun, 22 Jun 2025 12:50:27 +0300 Subject: [PATCH] bdk: display: update comments And also set WinD reg updating to HSYNC --- bdk/display/di.c | 33 +++++++++++++++------------------ bdk/display/di.h | 10 ++++++---- bdk/display/di.inl | 5 +++-- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/bdk/display/di.c b/bdk/display/di.c index 3eaf922d..3dbb0491 100644 --- a/bdk/display/di.c +++ b/bdk/display/di.c @@ -20,7 +20,6 @@ #include "di.h" #include #include -#include #include #include #include @@ -132,7 +131,6 @@ static void _display_dsi_read_rx_fifo(u32 *data) int display_dsi_read(u8 cmd, u32 len, void *data) { - int res = 0; u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0}; // Drain RX FIFO. @@ -181,14 +179,13 @@ int display_dsi_read(u8 cmd, u32 len, void *data) case ACK_ERROR_RES: default: - res = 1; - break; + return 1; } } else - res = 1; + return 1; - return res; + return 0; } int display_dsi_vblank_read(u8 cmd, u32 len, void *data) @@ -375,7 +372,7 @@ void display_init() CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = CLK_SRC_DIV(6); // Set PLLP_OUT and div 6 (68MHz). - // Bring every IO rail out of deep power down. + // Bring every IO rail out of deep power down. (Though no rail bit is set.) PMC(APBDEV_PMC_IO_DPD_REQ) = PMC_IO_DPD_REQ_DPD_OFF; PMC(APBDEV_PMC_IO_DPD2_REQ) = PMC_IO_DPD_REQ_DPD_OFF; @@ -414,9 +411,9 @@ void display_init() APB_MISC(APB_MISC_GP_DSI_PAD_CONTROL) = 0; } - // Set DISP1 clock source, parent clock and DSI/PCLK to low power mode. - // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz) - // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-PCLK): 48.9 MHz. (PCLK: 16.30 MHz) + // Set DISP1 clock source, parent clock and DSI/PCLK to command mode. + // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-BCLK): 50.0 MHz. (PCLK: 16.66 MHz) + // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-BCLK): 48.9 MHz. (PCLK: 16.30 MHz) clock_enable_plld(3, 20, true, tegra_t210); // Setup Display Interface initial window configuration. @@ -538,11 +535,11 @@ void display_init() // Unblank display. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000); - // Setup final dsi clock. - // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 468.0 MHz, PLLD_OUT0 (DSI): 234.0 MHz. + // Switch to DSI HS mode. + // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 468.0 MHz, PLLD_OUT0 (DSI-BCLK): 234.0 MHz. (PCLK: 78 MHz) clock_enable_plld(1, 24, false, tegra_t210); - // Finalize DSI init packet sequence configuration. + // Set HS PHY timing and finalize DSI packet sequence configuration. reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_video_non_burst_no_eot_config, ARRAY_SIZE(_di_dsi_seq_pkt_video_non_burst_no_eot_config)); // Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate. @@ -569,8 +566,8 @@ void display_init() // Set pad trimmers and set MIPI DSI cal offsets. if (tegra_t210) { - reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210)); - reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210)); + reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210)); + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210)); } else { @@ -700,9 +697,9 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) // De-initialize video controller. reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, ARRAY_SIZE(_di_dc_video_disable_config)); - // Set DISP1 clock source, parent clock and DSI/PCLK to low power mode. - // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz) - // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-PCLK): 48.9 MHz. (PCLK: 16.30 MHz) + // Set DISP1 clock source, parent clock and DSI/PCLK to command mode. + // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-BCLK): 50.0 MHz. (PCLK: 16.66 MHz) + // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-BCLK): 48.9 MHz. (PCLK: 16.30 MHz) clock_enable_plld(3, 20, true, hw_get_chip_id() == GP_HIDREV_MAJOR_T210); // Set timings for lowpower clocks. diff --git a/bdk/display/di.h b/bdk/display/di.h index 9a35d4ff..2dccd756 100644 --- a/bdk/display/di.h +++ b/bdk/display/di.h @@ -730,7 +730,7 @@ #define MIPI_DCS_PRIV_UNK_D9 0xD9 #define MIPI_DCS_PRIV_SM_DISPLAY_ID 0xDD // LVL1 LVL2 LVL3 UNK0 UNK1 -#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2 // Samsung: Lock (default): 5A5A A5A5 A5A5 A500 A500. Unlock: A5A5 5A5A 5A5A UNK UNK. +#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2 // Samsung: Lock (default): 5A5A A5A5 A5A5 A500 A500. Lock/Unlock: A5/5A. LVL1 group is normal registers. #define MIPI_DCS_PRIV_READ_EXTC_CMD_SPI 0xFE // Read EXTC Command In SPI. 1 byte. 0-6: EXT_SPI_CNT, 7:EXT_SP. #define MIPI_DCS_PRIV_SET_EXTC_CMD_REG 0xFF // EXTC Command Set enable register. 5 bytes. Pass: FF 98 06 04, PAGE. @@ -842,8 +842,8 @@ enum { PANEL_JDI_XXX062M = 0x10, - PANEL_JDI_LAM062M109A = 0x0910, - PANEL_JDI_LPM062M326A = 0x2610, + PANEL_JDI_LAM062M109A = 0x0910, // SI. + PANEL_JDI_LPM062M326A = 0x2610, // LTPS. PANEL_INL_P062CCA_AZ1 = 0x0F20, PANEL_AUO_A062TAN01 = 0x0F30, PANEL_INL_2J055IA_27A = 0x1020, @@ -851,12 +851,14 @@ enum PANEL_SHP_LQ055T1SW10 = 0x1040, PANEL_SAM_AMS699VC01 = 0x2050, - // Found on 6/2" clones. Unknown markings. Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F]. + // Found on 6/2" clones. Unknown markings. Clone of AUO A062TAN01. + // Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F]. Sometimes reports [30] 94 [0F]. Both IDs have correct CRC16. PANEL_OEM_CLONE_6_2 = 0x0F83, // Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings. PANEL_OEM_CLONE_5_5 = 0x00B3, // Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings. PANEL_OEM_CLONE = 0x0000 + //0x0F40 [40] 94 [0F], 5.5" clone }; void display_init(); diff --git a/bdk/display/di.inl b/bdk/display/di.inl index d74130e1..4923e43e 100644 --- a/bdk/display/di.inl +++ b/bdk/display/di.inl @@ -20,7 +20,7 @@ static const reg_cfg_t _di_dc_setup_win_config[] = { {DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_REG_ACT_CONTROL, WIN_A_ACT_HCNTR_SEL | WIN_B_ACT_HCNTR_SEL | WIN_C_ACT_HCNTR_SEL}, + {DC_CMD_REG_ACT_CONTROL, WIN_A_ACT_HCNTR_SEL | WIN_B_ACT_HCNTR_SEL | WIN_C_ACT_HCNTR_SEL | WIN_D_ACT_HCNTR_SEL}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, @@ -197,7 +197,7 @@ static const reg_cfg_t _di_dsi_panel_init_config_jdi[] = { {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -// DSI packet config. +// DSI HS packet config. static const reg_cfg_t _di_dsi_seq_pkt_video_non_burst_no_eot_config[] = { {DSI_PAD_CONTROL_1, 0}, @@ -211,6 +211,7 @@ static const reg_cfg_t _di_dsi_seq_pkt_video_non_burst_no_eot_config[] = { {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, + /* DSI packet sequence */ {DSI_PKT_SEQ_0_LO, 0x40000208}, {DSI_PKT_SEQ_2_LO, 0x40000308}, {DSI_PKT_SEQ_4_LO, 0x40000308},