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bdk: ccplex: do not disable mselect on cpu pwrgate

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CTCaer
2025-12-25 12:51:37 +02:00
parent 69ab954119
commit 0cab56293d
1 changed files with 1 additions and 3 deletions
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4
bdk/soc/ccplex.c
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@@ -146,8 +146,6 @@ void ccplex_powergate_cpu0()
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(30) | BIT(24) | BIT(16) | BIT(0); CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(30) | BIT(24) | BIT(16) | BIT(0);
// Set NONCPU reset. // Set NONCPU reset.
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(29); CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(29);
// Set MSELECT reset.
CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_SET) = BIT(CLK_V_MSELECT);
// Disable CE0. // Disable CE0.
pmc_domain_pwrgate_set(POWER_RAIL_CE0, DISABLE); pmc_domain_pwrgate_set(POWER_RAIL_CE0, DISABLE);
@@ -159,7 +157,7 @@ void ccplex_powergate_cpu0()
clock_disable_coresight(); clock_disable_coresight();
// Clear out MSELECT and CPU clocks. // Clear out MSELECT and CPU clocks.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_CLR) = BIT(CLK_V_MSELECT) | BIT(CLK_V_CPUG); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_CLR) = BIT(CLK_V_CPUG);
_ccplex_disable_power(); _ccplex_disable_power();
} }