diff --git a/bdk/input/touch.c b/bdk/input/touch.c
index f5b50987..2d6ef034 100644
--- a/bdk/input/touch.c
+++ b/bdk/input/touch.c
@@ -1,5 +1,5 @@
 /*
- * Touch driver for Nintendo Switch's STM FingerTip S (4CD60D) touch controller
+ * Touch driver for Nintendo Switch's STM FingerTip S (FTM4CD60DA1BE/FTM4CD50TA1BE) touch controller
  *
  * Copyright (c) 2018 langerhans
  * Copyright (c) 2018-2023 CTCaer
@@ -458,4 +458,4 @@ void touch_power_off()
 	max7762x_regulator_enable(REGULATOR_LDO6, false);
 
 	clock_disable_i2c(I2C_3);
-}
\ No newline at end of file
+}
diff --git a/bdk/mem/mc.c b/bdk/mem/mc.c
index 4e6ede60..869aef69 100644
--- a/bdk/mem/mc.c
+++ b/bdk/mem/mc.c
@@ -74,6 +74,7 @@ void mc_config_carveout()
 									 SEC_CARVEOUT_CFG_WR_NS;
 }
 
+// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
 void mc_enable_ahb_redirect()
 {
 	// Enable ARC_CLK_OVR_ON.
diff --git a/bdk/power/bq24193.h b/bdk/power/bq24193.h
index 4dfda4f3..9a939ba4 100644
--- a/bdk/power/bq24193.h
+++ b/bdk/power/bq24193.h
@@ -19,6 +19,8 @@
 #ifndef __BQ24193_H_
 #define __BQ24193_H_
 
+#include <utils/types.h>
+
 #define BQ24193_I2C_ADDR 0x6B
 
 // REG 0 masks.
diff --git a/bdk/soc/fuse.h b/bdk/soc/fuse.h
index 48a2c7fe..a417503d 100644
--- a/bdk/soc/fuse.h
+++ b/bdk/soc/fuse.h
@@ -34,6 +34,8 @@
 #define FUSE_PRIV2INTFC                       0x20
 #define FUSE_FUSEBYPASS                       0x24
 #define FUSE_PRIVATEKEYDISABLE                0x28
+#define  FUSE_PRIVKEY_DISABLE                  BIT(0)
+#define  FUSE_PRIVKEY_TZ_STICKY_BIT            BIT(4)
 #define FUSE_DISABLEREGPROGRAM                0x2C
 #define FUSE_WRITE_ACCESS_SW                  0x30
 #define FUSE_PWR_GOOD_SW                      0x34
diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c
index 7bfa599f..5b439128 100644
--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@@ -266,6 +266,9 @@ static void _config_se_brom()
 	// Try to set SBK from fuses. If patched, skip.
 	fuse_set_sbk();
 
+	// Make SBK unreadable.
+	//FUSE(FUSE_PRIVATEKEYDISABLE) = FUSE_PRIVKEY_TZ_STICKY_BIT | FUSE_PRIVKEY_DISABLE;
+
 	// Lock SSK (although it's not set and unused anyways).
 	// se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
 
@@ -365,9 +368,8 @@ void hw_init()
 	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
 	bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG;
 
-	// Bootrom stuff we skipped by going through rcm.
+	// Bootrom stuff we might skipped by going through rcm.
 	_config_se_brom();
-	//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
 
 	// Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
 	SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F;
@@ -422,9 +424,10 @@ void hw_init()
 	// Set BPMP/SCLK to PLLP_OUT (408MHz).
 	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333;
 
-	// Power on T210B01 shadow TZRAM and lock the reg.
+	// Disable T210B01 TZRAM power-gating and lock the reg.
 	if (!tegra_t210)
 	{
+		// This is not actually needed since it's done by bootrom. The read locks are extra.
 		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL)      &= ~PMC_TZRAM_PWR_CNTRL_SD;
 		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
 		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE)     = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
diff --git a/bdk/soc/pmc.h b/bdk/soc/pmc.h
index 57218959..ea8aaa9d 100644
--- a/bdk/soc/pmc.h
+++ b/bdk/soc/pmc.h
@@ -154,6 +154,8 @@
 #define APBDEV_PMC_SCRATCH188        0x810
 #define APBDEV_PMC_SCRATCH190        0x818
 #define APBDEV_PMC_SCRATCH200        0x840
+#define  PMC_NX_PANIC_SAFE_MODE            0x20
+#define  PMC_NX_PANIC_BYPASS_FUSES         0x21
 #define APBDEV_PMC_SCRATCH201        0x844
 #define APBDEV_PMC_SCRATCH250        0x908
 #define APBDEV_PMC_SECURE_SCRATCH108 0xB08
diff --git a/bdk/storage/nx_emmc_bis.h b/bdk/storage/nx_emmc_bis.h
index 7cdacfc1..58413588 100644
--- a/bdk/storage/nx_emmc_bis.h
+++ b/bdk/storage/nx_emmc_bis.h
@@ -21,6 +21,8 @@
 #include <storage/emmc.h>
 #include <storage/sdmmc.h>
 
+#define NAND_PATROL_SECTOR   0xC20
+
 typedef struct _nx_emmc_cal0_spk_t
 {
 	u16 unk0;
@@ -65,13 +67,18 @@ typedef struct _nx_emmc_cal0_spk_t
 
 typedef struct _nx_emmc_cal0_t
 {
+	// Header.
 	u32  magic; // 'CAL0'.
 	u32  version;
 	u32  body_size;
 	u16  model;
 	u16  update_cnt;
-	u8   pad_crc16_0[0x10];
+	u8   pad_crc16_hdr[0x10];
+
+	// SHA256 for body.
 	u8   body_sha256[0x20];
+
+	// Body.
 	char cfg_id1[0x1E];
 	u8   crc16_pad1[2];
 	u8   rsvd0[0x20];
@@ -225,6 +232,7 @@ typedef struct _nx_emmc_cal0_t
 
 	// 10.0.0 and up.
 	u8   console_6axis_sensor_mount_type;
+	u8   crc16_pad61[0xF];
 } __attribute__((packed)) nx_emmc_cal0_t;
 
 int  nx_emmc_bis_read(u32 sector, u32 count, void *buff);
diff --git a/bdk/thermal/tmp451.c b/bdk/thermal/tmp451.c
index 65f2fd24..0586cd4c 100644
--- a/bdk/thermal/tmp451.c
+++ b/bdk/thermal/tmp451.c
@@ -21,6 +21,7 @@
 #include <soc/t210.h>
 #include <thermal/tmp451.h>
 
+// Remote Sensor.
 u16 tmp451_get_soc_temp(bool intenger)
 {
 	u8 val;
@@ -37,6 +38,7 @@ u16 tmp451_get_soc_temp(bool intenger)
 	return temp;
 }
 
+// Local Sensor.
 u16 tmp451_get_pcb_temp(bool intenger)
 {
 	u8 val;
@@ -72,7 +74,7 @@ void tmp451_init()
 		i2c_send_byte(I2C_1, TMP451_I2C_ADDR, TMP451_SOC_TMP_OFL_REG, 0x80); // + 0.5 oC.
 	}
 
-	// Set conversion rate to 32/s and make a read to update the reg.
+	// Set conversion rate to 31 ms and make a read to update the reg.
 	i2c_send_byte(I2C_1, TMP451_I2C_ADDR, TMP451_CNV_RATE_REG, 9);
 	tmp451_get_soc_temp(false);
 
diff --git a/bdk/utils/util.c b/bdk/utils/util.c
index 69498aca..b7a60518 100644
--- a/bdk/utils/util.c
+++ b/bdk/utils/util.c
@@ -287,7 +287,7 @@ void power_set_state(power_state_t state)
 		break;
 
 	case REBOOT_BYPASS_FUSES:
-		panic(0x21); // Bypass fuse programming in package1.
+		panic(PMC_NX_PANIC_BYPASS_FUSES); // Bypass fuse programming in package1.
 		break;
 
 	case POWER_OFF: