OmniNX/hekate-pro
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2,080 Commits 3 Branches 63 Tags
d086da50d734d46eacc6d7a170dbe8aa974b73ed
Commit Graph

98 Commits

Author SHA1 Message Date
CTCaer
e7deafd6a1 bdk: smmu: reset heap on disable 
And rename domain init/deinit
 2026-03-27 20:42:31 +01:00
CTCaer
3e6df2459d bdk: sdram: add missing T210 1GB density timings 2026-03-27 20:42:31 +01:00
CTCaer
a02624cd39 bdk: mc: reduce ahb aperture by 4KB 
The state machine automatically uses TOM + 4KB as real top address.
This can cause issues with HW that accesses that low RAM range,
since once the request enters ARC can't be redirected to MC and can hang.
 2026-03-27 20:42:31 +01:00
CTCaer
88ba35b73f bdk: mc: always enable ahb redirection 2026-03-27 20:42:31 +01:00
CTCaer
45446486f2 bdk: dram: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
378d38b850 bdk: add missing header guards 2026-03-27 19:38:45 +01:00
CTCaer
f155346238 bdk: ianos: restructure for future expansion 2026-03-27 19:38:08 +01:00
CTCaer
9ebd03802f bdk: heap: use ultra fast defragmentation 
The defragmentation runs on every free and it only merges subsequent nodes.
So there's no point of looping all nodes.
So, just check if previous and next nodes are mergeable.
This makes free performant and achieves the same exact functionality.
 2026-03-27 09:59:42 +01:00
CTCaer
8220466523 bdk: heap: add more safe guards 
- Use magic for used regions
- Deduplicate calloc
Enable a print/abort in _heap_free() for debugging.
 2026-03-27 09:57:59 +01:00
CTCaer
76922b7b87 bdk: minerva: add IRB support 
Aka no table support.
 2026-03-27 09:55:12 +01:00
CTCaer
b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer
ac245a0b6f bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2026-03-27 09:51:46 +01:00
CTCaer
877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer
0fa5db1d74 bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2026-03-27 09:48:53 +01:00
CTCaer
e19cf3038b bdk: minerva: allow sdmmc la to be skipped on L4T 2026-03-27 09:44:07 +01:00
CTCaer
030576ff3f bdk: mc: carveouts are not set by cfg so fix them 
For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them.
So add which need different value from reset and also make sure that data is flushed for WPR config.
 2026-03-27 09:44:07 +01:00
CTCaer
44e4c0ab21 bdk: make use of new MC/EMC defines 2026-03-27 09:44:07 +01:00
CTCaer
f45adfd92f bdk: rework MC/EMC register defines from scratch 
And add register structs also.
 2026-03-27 09:44:06 +01:00
CTCaer
380c1dc9b2 bdk: refactor several comments and defines 2026-03-27 09:05:58 +01:00
CTCaer
fbaa88cc31 bdk: smmu: add smmu disable 2026-03-27 09:05:58 +01:00
CTCaer
2d91e9b549 bdk: clock: refactor common PLL defines 2026-03-27 09:05:58 +01:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
716cfbfbaf bdk: sdram: refactor init 2024-07-02 18:02:05 +03:00
CTCaer
655209bedc bdk: sdram: keep sdmmc1 no iopower state 2024-06-08 12:19:24 +03:00
CTCaer
14706cef4e bdk: minerva: add emc src div disable 2024-06-02 06:46:28 +03:00
CTCaer
2648a2655c bdk: sdram: add info about custom 8GB T210 config 
That's a suggestion on which 4GB modules are certainly fine to use.
 2024-04-25 04:50:07 +03:00
CTCaer
e846f4576e bdk: minerva: l4t: adjust sdmmc1 la and freq table 
- LA is tightened up
- Copied frequencies are now 204/408/800/1333/1600/OC (from 204/666/800/1600/OC)
 2024-03-29 13:21:53 +02:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759 bdk: smmu: refactor and update driver 
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
 2024-03-14 09:21:06 +02:00
CTCaer
9a520d63a6 bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
CTCaer
3a4fa12f42 bdk: smmu: powergate ccplex after enabling smmu 2024-03-13 01:44:58 +02:00
CTCaer
fb31cb2926 bdk: ccplex: add no rst vector lock & powergating 
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
 2024-03-13 01:37:52 +02:00
CTCaer
4131ff12d7 bdk: sdram: adjust sdmmc1 la for l4t 2024-02-21 10:50:15 +02:00
CTCaer
644747230c bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
CTCaer
1f30b8deb7 bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
CTCaer
4576ed81ef sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
CTCaer
b37430dc1d bdk: update copyright year 2024-01-07 12:38:10 +02:00
CTCaer
75543875e2 bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
CTCaer
30c320d6e7 bdk: sdram: update all ram info comments 2024-01-06 22:05:24 +02:00
CTCaer
eff27d92f2 bdk: sdram: update default wpr overrides 
Since it's only used in L4T set them to the correct latest reg tool values.

HOS overrides them anyway.
 2024-01-06 22:03:54 +02:00
CTCaer
3874840d77 bdk: sdram: update cfg for 8GB erista 2024-01-06 21:59:18 +02:00
CTCaer
74e252aaf2 bdk: sdram: update latest reg tool vpr overrides 
Set them to default config and remove them from patching.
 2024-01-06 21:58:51 +02:00
CTCaer
2cc6cd45d9 bdk: dram: small refactor 2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
CTCaer
bb6e4deb4c bdk: remove unused lp0 cfg from bdk 2023-12-27 21:02:33 +02:00
CTCaer
913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram 
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
 2023-12-25 03:02:11 +02:00
CTCaer
ce42e27f45 bdk: minerva: do not handle oc freq 
Arachne already handles it.
 2023-08-22 16:44:41 +03:00
CTCaer
d73a3fdd7c bdk: sdram: name 1a micron ram chips 
Again, as with 3rd gen samsung and hynix, that's an educated guess.
 2023-08-22 14:44:27 +03:00
CTCaer
1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer
b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00