Commit Graph

36 Commits

Author SHA1 Message Date
CTCaer
925b6e22bb bdk: se: add T210 SHA256 silicon errata WAR
Apparently, some T210 silicon have an undocumented errata where the MSG_LEFT2/3
registers are not ignored as they should.
When they have random data in POR they cause a hang as long as the message and
SHA calculation speed. So always clear them.
Additionally, clear MSG_LENGTH2/3 registers too even though they do not matter.
2026-03-27 10:02:21 +01:00
CTCaer
5a35a61753 bdk: se: adjust T210 silicon errata coherency WAR
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
2026-03-27 10:02:21 +01:00
CTCaer
e649d1df8e bdk: se: correct result for < block size aes 2026-03-27 10:02:21 +01:00
CTCaer
8e2a776e73 bdk: se: support multiple/partial blocks for RNG 2026-03-27 09:59:42 +01:00
CTCaer
d0dcfd0008 bdk: se: use proper naming for ctx keys 2026-03-27 09:59:42 +01:00
CTCaer
a258c726dc bdk: se: refactor and optimize SHA256
- Simplify config and fix partial hashing
- Add partial function calls
- All partial state is handled internally
- All functions now use the classic naming convention.
2026-03-27 09:59:42 +01:00
CTCaer
89795a4c96 bdk: se: use classic naming convention for XTS 2026-03-27 09:59:42 +01:00
CTCaer
5a40f26010 bdk: se: add AES OFB encryption/decryption support 2026-03-27 09:59:42 +01:00
CTCaer
6c7370bec3 bdk: se: remove dst/src size argument requirement
All operations expect the destination buffer to fit the selected size.
And for simplicity STATE_WAIT is not supported.

Additionally, remove single block ECB and just use the normal function.
2026-03-27 09:59:42 +01:00
CTCaer
ba71fb0dba bdk: se: optimize and update aes cmac hashing
`se_aes_cmac_128` was also renamed to `se_aes_hash_cmac`.
By following the convention of 128bit functions not having size in their name.
2026-03-27 09:59:42 +01:00
CTCaer
d1066da9fa bdk: se: handle original and updated IV in one go
IV set now requires a size where the second block is updated IV
IV clear now clears both.
2026-03-27 09:59:42 +01:00
CTCaer
542fba6fbd bdk: se: support partial blocks for all aes modes 2026-03-27 09:59:42 +01:00
CTCaer
1295152f20 bdk: se: do a trivial refactor pass 2026-03-27 09:59:42 +01:00
CTCaer
74833e19e7 bdk: se: heap is not used anymore 2025-05-13 16:27:09 +02:00
CTCaer
e8addedd2f bdk: se: add 0 byte sha256 support 2025-05-13 16:17:40 +02:00
CTCaer
c8acea7ad5 bdk: se: remove malloc usage 2025-05-13 16:08:42 +02:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
92093ff08e bdk: se: deduplicate sha hash extraction 2023-12-27 21:07:52 +02:00
CTCaer
e47a819948 bdk: se: add more useful functions
- aes cmac 128bit
- aes hashing
- option to clear updated aes iv
2023-12-25 03:44:52 +02:00
CTCaer
9a98c1afb9 bdk: stylistic corrections
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
b65b2d7f71 bdk: se: do not use heap for linked lists 2022-06-27 09:14:43 +03:00
CTCaer
7c74391754 bdk: bpmp: do not use full maintenance
Instead use proper clean/invalidation of dcache.
2022-02-15 00:14:14 +02:00
CTCaer
c1441a64c7 bdk: se: expose xts functions and add nx xts 2022-01-20 12:28:26 +02:00
CTCaer
0e35e68fd5 bdk: se: add t210b01 data coherency WAR 2022-01-20 12:27:25 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
9541d1bbd3 se: add encrypt/decrypt defines 2021-08-28 16:40:29 +03:00
CTCaer
a7bf8bf118 se: Refactor with proper names
Additionally fix some bugs in rsa access control
2021-02-06 02:55:58 +02:00
CTCaer
5b8fb9fb6b Various refactoring and addition of comments 2020-12-11 17:25:59 +02:00
CTCaer
8249d9e1a2 se: Ensure aligned key/iv/ctr/hash copy 2020-12-05 20:39:17 +02:00
CTCaer
cabaa6cfb8 Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
CTCaer
88fa4fa861 se: Add set/clear IV and aes key get 2020-07-18 00:36:51 +03:00
CTCaer
6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer
185526d134 Introducing Bootloader Development Kit (BDK)
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.

Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.

Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.

This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00