OmniNX/hekate-pro
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4b796ab63fe9bff8f92612a4a99669c16a995ffa
Commit Graph

117 Commits

Author SHA1 Message Date
CTCaer
ef0ab0b0f1 bdk: sdmmc: correct drive ohms comment 2026-03-27 09:51:47 +01:00
CTCaer
fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer
6cc3aee389 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2026-03-27 09:44:07 +01:00
CTCaer
baea3b0265 bdk: use f_unmount instead of null f_mount 2026-03-27 09:07:45 +01:00
CTCaer
380c1dc9b2 bdk: refactor several comments and defines 2026-03-27 09:05:58 +01:00
Christoph Baumann
bc42579f01 boot_storage_mount: only deinitialize storage, if it wasnt initialized to begin with 2025-10-09 12:36:35 +02:00
Christoph Baumann
d6fda80057 remove prints, fix backup/restore 2025-05-21 12:31:17 +02:00
Christoph Baumann
9b95d026f3 support for file based and sd partition based emusd 2025-05-20 00:40:48 +02:00
Christoph Baumann
154ed594fc Support for hekate to boot hos with emusd/emmc base emummc 2025-05-14 02:24:33 +02:00
CTCaer
8978ba9e54 bdk: mc: fix warning for arbiter check 2025-05-13 16:27:15 +02:00
CTCaer
3412714402 bdk: sdmmc: add extention regs read/parse 2025-05-13 16:16:45 +02:00
CTCaer
4c4a63795e bdk: sdmmc: refactor error checking on rw 
And also check if card status is ok after a read/write.
 2025-05-13 16:11:13 +02:00
CTCaer
04dc8d2a86 bdk: sdmmc: check that cmd timed out if SDSC 
Instead of assuming that, check it.
This fix will make SDUC not to be assumed as SDSC.
 2025-05-13 16:10:59 +02:00
CTCaer
ed4b638545 bdk: sdmmc: update unstuff_bits to use mod 
Since unstuff_bits only supports 128bits, instead of subtracting the correct amount of bits with the offset array, use % 128.
 2025-05-13 16:10:48 +02:00
CTCaer
1e54d538fd bdk: sdmmc: small refactor 2025-05-13 16:10:13 +02:00
CTCaer
20487cb8b9 bdk: sdmmc: check for out bounds access 2025-05-13 16:09:06 +02:00
Christoph Baumann
76508c74e8 file based emmc emummc, some other stuff 2025-05-12 01:24:01 +02:00
Christoph Baumann
0a7a004839 file based emummc on emmc 2025-05-08 01:48:04 +02:00
Christoph Baumann
7521055bec fix name 2025-05-07 17:29:04 +02:00
Christoph Baumann
4bfe1fe2cd add missing fsync 2025-05-07 17:27:58 +02:00
Christoph Baumann
6d09e65d85 fix emummc bis 2025-05-07 16:46:48 +02:00
Christoph Baumann
e5ceb4a2de add mmc types for emummc, used only for emummc ums 2025-05-07 16:45:26 +02:00
Christoph Baumann
942e7defe3 add methods to access file based emummc 2025-05-07 16:42:36 +02:00
Christoph Baumann
39b74dd50d file based bis support 2025-05-07 12:17:13 +02:00
Christoph Baumann
241b0f2274 . 2025-05-06 12:37:46 +02:00
Christoph Baumann
7941a3d4d6 fix boot storage selection 2025-05-02 17:07:42 +02:00
Christoph Baumann
4f72660603 fuck 2025-05-02 01:43:51 +02:00
Christoph Baumann
2440318cb5 emmc bis storage 2025-04-30 11:29:06 +02:00
Christoph Baumann
28796b417b fix indicators, add emmc_mount, various fixes 2025-04-29 12:36:32 +02:00
Christoph Baumann
337f219ac6 Support for NYX to load from BOOT1/GPP/SD in that order, UMS option to mount whatever volume is selected as boot storage 2025-04-24 12:06:15 +02:00
Christoph Baumann
4e9e21b3b1 move boot_storage.h/.c to bdk/storage, check result of ensure_partition 2025-04-22 14:25:14 +02:00
Christoph Baumann
5798dcde0d Add support for reading boot files from FAT partition on BOOT1/GPP/SD in that order 
Emummc config is read from boot partition, file based files still read from SD
 2025-04-22 13:42:20 +02:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
75a4a8ba1d bdk: sdmmc: remove higher power limits 
UHS-I Cards force a max of 1.44W even if higher modes are selected.
This does not change functionality, so remove them as unused.
 2024-06-10 13:37:28 +03:00
CTCaer
a37b5c7841 bdk: sdmmc: no need to raise power limit for HS25 2024-06-10 13:24:07 +03:00
CTCaer
48334779a5 bdk: sdmmc: error reporting changes 
- Correct transfer error message
- Add debug print for deinit
 2024-06-08 17:41:11 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
a34206df5b bdk: sdmmc: small changes 
- Log warning for comp pad calibration timeout
- Rename some func/defines
- Increase SDMMC1 power disable wait to 10ms
 No real perceived functionality change.
 2024-06-07 17:09:30 +03:00
CTCaer
9d79af231e bdk: use static where it should 2024-06-02 07:09:34 +03:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
f126486266 bdk: sdmmc: utilize block size defines 2024-03-12 15:47:14 +02:00
CTCaer
41d3565353 bdk: sdmmc: deduplicate function modes get 
And parse the whole info
 2023-12-27 15:01:20 +02:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer
820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00