OmniNX/hekate-pro
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,964 Commits 3 Branches 63 Tags
1295152f20c96f18985534f79c2c74a9c2c3a83a
Commit Graph

591 Commits

Author SHA1 Message Date
CTCaer
1295152f20 bdk: se: do a trivial refactor pass 2026-03-27 09:59:42 +01:00
CTCaer
9ebd03802f bdk: heap: use ultra fast defragmentation 
The defragmentation runs on every free and it only merges subsequent nodes.
So there's no point of looping all nodes.
So, just check if previous and next nodes are mergeable.
This makes free performant and achieves the same exact functionality.
 2026-03-27 09:59:42 +01:00
CTCaer
d391ef3b0f bdk: max17050: simplify calculations 
And make current readings a tiny bit (±0.16%) more accurate.
 2026-03-27 09:58:48 +01:00
CTCaer
9ef684037b bdk: max17050: remove unused cached batt voltage 2026-03-27 09:58:48 +01:00
CTCaer
19279fa57d bdk: joycon: improve charger config 
Utilize charger config set command which allows for supplement mode.
Additionally, remove ping config when SIO and parse buttons/sticks on subcmd reports.
 2026-03-27 09:58:48 +01:00
CTCaer
2004b38f41 bdk: ccplex: do not disable mselect on cpu pwrgate 2026-03-27 09:57:59 +01:00
CTCaer
8220466523 bdk: heap: add more safe guards 
- Use magic for used regions
- Deduplicate calloc
Enable a print/abort in _heap_free() for debugging.
 2026-03-27 09:57:59 +01:00
CTCaer
d379a17444 bdk: display: improve and deduplicate more 
- Add delay after a DSI soft reset
- Remove more duplicated configs
- Improve code to save code size
- Improve comments
- Do not allow display_backlight to be used with OLED
 2026-03-27 09:57:59 +01:00
CTCaer
db4c6a0b69 bdk: util: use volatile base for reg_write_array 2026-03-27 09:57:59 +01:00
CTCaer
8b86bf3808 bdk: display: use a scratch reg for backlight 
Spare registers normally have hidden hw config usage, so avoid them just in case.
 2026-03-27 09:57:59 +01:00
CTCaer
46fa18be89 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2026-03-27 09:57:59 +01:00
CTCaer
c17881f2c3 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2026-03-27 09:57:59 +01:00
CTCaer
c907d143b7 bdk: fatfs: improve fat read/write 
- Convert access from min cluster size to block size
  Also allow read/writes to less than cluster size
- In case of intercluster access throw an error
- Do not error on zero size

On reads buffer still needs to be block (instead of cluster) aligned.
On writes, buffer still needs to be readable out of bounds.
 2026-03-27 09:57:59 +01:00
CTCaer
ffc0aa2c3d bdk: fuse: return array size with fuse_read_array 2026-03-27 09:57:23 +01:00
CTCaer
76922b7b87 bdk: minerva: add IRB support 
Aka no table support.
 2026-03-27 09:55:12 +01:00
CTCaer
03cb1aac29 bdk: clock: update some defines 2026-03-27 09:54:06 +01:00
CTCaer
61cb77a016 bdk: sdmmc: add defines for max block number 2026-03-27 09:54:06 +01:00
CTCaer
8d525a3c50 bdk: add reserved cfg to ipl meta and nyx storage 2026-03-27 09:51:47 +01:00
CTCaer
ef0ab0b0f1 bdk: sdmmc: correct drive ohms comment 2026-03-27 09:51:47 +01:00
CTCaer
7b7906efc2 bdk: clock: add i2c to the errata affected list 2026-03-27 09:51:47 +01:00
CTCaer
e29d139946 bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2026-03-27 09:51:47 +01:00
CTCaer
b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer
11b49e3bbc bdk: nyx: rename disp_id to panel_id 2026-03-27 09:51:46 +01:00
CTCaer
ac245a0b6f bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2026-03-27 09:51:46 +01:00
CTCaer
c0300b1cee bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2026-03-27 09:51:46 +01:00
CTCaer
1eaa801d6a bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2026-03-27 09:51:46 +01:00
CTCaer
25359b23b9 bdk: clock: add sdmmc1 to the errata affected list 2026-03-27 09:51:46 +01:00
CTCaer
db08514ff0 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2026-03-27 09:51:46 +01:00
CTCaer
877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer
fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer
ac0d98ad29 bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2026-03-27 09:51:46 +01:00
CTCaer
a365af0492 bdk: bpmp: add binX clock defines 2026-03-27 09:48:54 +01:00
CTCaer
28dce16877 bdk: fuse: add sense function 2026-03-27 09:48:54 +01:00
CTCaer
f541f14699 bdk: fuse: add extra info on regs 2026-03-27 09:48:54 +01:00
CTCaer
518cfd401a bdk: fuse: correct masking on array read cmd 2026-03-27 09:48:54 +01:00
CTCaer
44dd00c29a bdk: t210: add mc channel macros 2026-03-27 09:48:54 +01:00
CTCaer
0fa5db1d74 bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2026-03-27 09:48:53 +01:00
CTCaer
76d5cf591f bdk: lvgl: make sure task has a task to call 2026-03-27 09:48:53 +01:00
CTCaer
67157b1867 bdk: ini: switch back to ASCII ordering 
For combining multiple inis.
 2026-03-27 09:44:07 +01:00
CTCaer
af72bb5b94 bdk: dirlist: use flags instead of arguments 
A new flag was also added that forces an ASCII ordering instead of Alphabetical one.
 2026-03-27 09:44:07 +01:00
CTCaer
e19cf3038b bdk: minerva: allow sdmmc la to be skipped on L4T 2026-03-27 09:44:07 +01:00
CTCaer
b52f5edce6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2026-03-27 09:44:07 +01:00
CTCaer
393d135105 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2026-03-27 09:44:07 +01:00
CTCaer
6cc3aee389 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2026-03-27 09:44:07 +01:00
CTCaer
030576ff3f bdk: mc: carveouts are not set by cfg so fix them 
For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them.
So add which need different value from reset and also make sure that data is flushed for WPR config.
 2026-03-27 09:44:07 +01:00
CTCaer
44e4c0ab21 bdk: make use of new MC/EMC defines 2026-03-27 09:44:07 +01:00
CTCaer
f45adfd92f bdk: rework MC/EMC register defines from scratch 
And add register structs also.
 2026-03-27 09:44:06 +01:00
CTCaer
2fda4115aa bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2026-03-27 09:44:06 +01:00
CTCaer
d289224653 bdk: clock: simplify logic 
Simplify logic for clock enable and sdmmc clock management
 2026-03-27 09:44:06 +01:00
CTCaer
0647fd06d8 bdk: clock: remove non existent module ids 
And add comments to special handling ones
 2026-03-27 09:44:06 +01:00