Refactoring and comment adding

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CTCaer committed 2019-09-12 23:08:38 +03:00
1 parent c5b64a2b58
commit a8d529cf6a
47 files changed
+477 -300

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@@ -1263,7 +1263,8 @@ void ipl_main()
// Save sdram lp0 config.
if (!ianos_loader(false, "bootloader/sys/libsys_lp0.bso", DRAM_LIB, (void *)sdram_get_params_patched()))
h_cfg.errors |= ERR_LIBSYS_LP0;
// Train DRAM and switch to max frequency.
minerva_init();
minerva_change_freq(FREQ_1600);