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Update BDK to Hekate 6.0.5

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This commit is contained in:
suchmememanyskill
2023-07-20 16:45:07 +02:00
parent 09fc492610
commit ee6ea3e64c
103 changed files with 6271 additions and 3746 deletions
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16
bdk/storage/emmc.c
View File

@@ -61,6 +61,8 @@ u32 emmc_get_mode()
return emmc_mode;
}
void emmc_end() { sdmmc_storage_end(&emmc_storage); }
int emmc_init_retry(bool power_cycle)
{
u32 bus_width = SDMMC_BUS_WIDTH_8;
@@ -70,7 +72,7 @@ int emmc_init_retry(bool power_cycle)
if (power_cycle)
{
emmc_mode--;
sdmmc_storage_end(&emmc_storage);
emmc_end();
}
// Get init parameters.
@@ -105,7 +107,7 @@ bool emmc_initialize(bool power_cycle)
emmc_mode = EMMC_MMC_HS400;
if (power_cycle)
sdmmc_storage_end(&emmc_storage);
emmc_end();
int res = !emmc_init_retry(false);
@@ -124,11 +126,13 @@ bool emmc_initialize(bool power_cycle)
}
}
sdmmc_storage_end(&emmc_storage);
emmc_end();
return false;
}
int emmc_set_partition(u32 partition) { return sdmmc_storage_set_mmc_partition(&emmc_storage, partition); }
void emmc_gpt_parse(link_t *gpt)
{
gpt_t *gpt_buf = (gpt_t *)calloc(GPT_NUM_BLOCKS, EMMC_BLOCKSIZE);
@@ -150,10 +154,10 @@ void emmc_gpt_parse(link_t *gpt)
if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba)
continue;
part->index = i;
part->index = i;
part->lba_start = gpt_buf->entries[i].lba_start;
part->lba_end = gpt_buf->entries[i].lba_end;
part->attrs = gpt_buf->entries[i].attrs;
part->lba_end = gpt_buf->entries[i].lba_end;
part->attrs = gpt_buf->entries[i].attrs;
// ASCII conversion. Copy only the LSByte of the UTF-16LE name.
for (u32 j = 0; j < 36; j++)

18
bdk/storage/emmc.h
View File

@@ -30,18 +30,18 @@
enum
{
EMMC_INIT_FAIL = 0,
EMMC_1BIT_HS52 = 1,
EMMC_8BIT_HS52 = 2,
EMMC_MMC_HS200 = 3,
EMMC_MMC_HS400 = 4,
EMMC_INIT_FAIL = 0,
EMMC_1BIT_HS52 = 1,
EMMC_8BIT_HS52 = 2,
EMMC_MMC_HS200 = 3,
EMMC_MMC_HS400 = 4,
};
enum
{
EMMC_ERROR_INIT_FAIL = 0,
EMMC_ERROR_RW_FAIL = 1,
EMMC_ERROR_RW_RETRY = 2
EMMC_ERROR_INIT_FAIL = 0,
EMMC_ERROR_RW_FAIL = 1,
EMMC_ERROR_RW_RETRY = 2
};
typedef struct _emmc_part_t
@@ -63,6 +63,8 @@ u16 *emmc_get_error_count();
u32 emmc_get_mode();
int emmc_init_retry(bool power_cycle);
bool emmc_initialize(bool power_cycle);
int emmc_set_partition(u32 partition);
void emmc_end();
void emmc_gpt_parse(link_t *gpt);
void emmc_gpt_free(link_t *gpt);

52
bdk/storage/mbr_gpt.h
View File

@@ -39,40 +39,40 @@ typedef struct _mbr_part_t
typedef struct _mbr_t
{
u8 bootstrap[440];
u32 signature;
u16 copy_protected;
mbr_part_t partitions[4];
u16 boot_signature;
/* 0x000 */ u8 bootstrap[440];
/* 0x1B8 */ u32 signature;
/* 0x1BC */ u16 copy_protected;
/* 0x1BE */ mbr_part_t partitions[4];
/* 0x1FE */ u16 boot_signature;
} __attribute__((packed)) mbr_t;
typedef struct _gpt_entry_t
{
u8 type_guid[0x10];
u8 part_guid[0x10];
u64 lba_start;
u64 lba_end;
u64 attrs;
u16 name[36];
/* 0x00 */ u8 type_guid[0x10];
/* 0x10 */ u8 part_guid[0x10];
/* 0x20 */ u64 lba_start;
/* 0x28 */ u64 lba_end;
/* 0x30 */ u64 attrs;
/* 0x38 */ u16 name[36];
} gpt_entry_t;
typedef struct _gpt_header_t
{
u64 signature; // "EFI PART"
u32 revision;
u32 size;
u32 crc32;
u32 res1;
u64 my_lba;
u64 alt_lba;
u64 first_use_lba;
u64 last_use_lba;
u8 disk_guid[0x10];
u64 part_ent_lba;
u32 num_part_ents;
u32 part_ent_size;
u32 part_ents_crc32;
u8 res2[420]; // Used as first 3 partition entries backup for HOS.
/* 0x00 */ u64 signature; // "EFI PART"
/* 0x08 */ u32 revision;
/* 0x0C */ u32 size;
/* 0x10 */ u32 crc32;
/* 0x14 */ u32 res1;
/* 0x18 */ u64 my_lba;
/* 0x20 */ u64 alt_lba;
/* 0x28 */ u64 first_use_lba;
/* 0x30 */ u64 last_use_lba;
/* 0x38 */ u8 disk_guid[0x10];
/* 0x48 */ u64 part_ent_lba;
/* 0x50 */ u32 num_part_ents;
/* 0x54 */ u32 part_ent_size;
/* 0x58 */ u32 part_ents_crc32;
/* 0x5C */ u8 res2[420]; // Used as first 3 partition entries backup for HOS.
} gpt_header_t;
typedef struct _gpt_t

5
bdk/storage/mmc.h
View File

@@ -408,7 +408,10 @@
/*
* BKOPS status level
*/
#define EXT_CSD_BKOPS_LEVEL_2 0x2
#define EXT_CSD_BKOPS_OK 0x0
#define EXT_CSD_BKOPS_NON_CRITICAL 0x1
#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2
#define EXT_CSD_BKOPS_CRITICAL 0x3
/*
* BKOPS modes

14
bdk/storage/nx_emmc_bis.c
View File

@@ -251,7 +251,12 @@ int nx_emmc_bis_read(u32 sector, u32 count, void *buff)
while (count)
{
u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS);
// Get sector index in cluster and use it as boundary check.
u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS);
cnt_max = BIS_CLUSTER_SECTORS - cnt_max;
u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
if (nx_emmc_bis_read_block(curr_sct, sct_cnt, buf))
return 0;
@@ -270,7 +275,12 @@ int nx_emmc_bis_write(u32 sector, u32 count, void *buff)
while (count)
{
u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS);
// Get sector index in cluster and use it as boundary check.
u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS);
cnt_max = BIS_CLUSTER_SECTORS - cnt_max;
u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
if (nx_emmc_bis_write_block(curr_sct, sct_cnt, buf, false))
return 0;

18
bdk/storage/nx_emmc_bis.h
View File

@@ -85,13 +85,13 @@ typedef struct _nx_emmc_cal0_t
u8 bd_mac[6];
u8 crc16_pad4[2];
u8 rsvd2[8];
u8 acc_offset[6];
u16 acc_offset[3];
u8 crc16_pad5[2];
u8 acc_scale[6];
u16 acc_scale[3];
u8 crc16_pad6[2];
u8 gyro_offset[6];
u16 gyro_offset[3];
u8 crc16_pad7[2];
u8 gyro_scale[6];
u16 gyro_scale[3];
u8 crc16_pad8[2];
char serial_number[0x18];
u8 crc16_pad9[8];
@@ -213,11 +213,15 @@ typedef struct _nx_emmc_cal0_t
// 6.0.0 and up.
u8 battery_ver;
u8 crc16_pad58[0x1F];
u8 crc16_pad58[0xF];
// 10.0.0 and up.
u8 touch_ic_vendor_id;
u8 crc16_pad59[0xF];
// 9.0.0 and up.
u32 home_menu_scheme_model;
u8 crc16_pad59[0xC];
u32 color_model;
u8 crc16_pad60[0xC];
// 10.0.0 and up.
u8 console_6axis_sensor_mount_type;

83
bdk/storage/sd.c
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2022 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -22,10 +22,18 @@
#include <libs/fatfs/ff.h>
#include <mem/heap.h>
#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT
#define SD_DEFAULT_SPEED SD_UHS_SDR104
#else
#define SD_DEFAULT_SPEED SD_UHS_DDR208
#endif
static bool sd_mounted = false;
static bool sd_init_done = false;
static bool insertion_event = false;
static u16 sd_errors[3] = { 0 }; // Init and Read/Write errors.
static u32 sd_mode = SD_UHS_SDR104;
static u32 sd_mode = SD_DEFAULT_SPEED;
sdmmc_t sd_sdmmc;
sdmmc_storage_t sd_storage;
@@ -54,7 +62,7 @@ u16 *sd_get_error_count()
bool sd_get_card_removed()
{
if (sd_init_done && !sdmmc_get_sd_inserted())
if (insertion_event && !sdmmc_get_sd_inserted())
return true;
return false;
@@ -78,7 +86,11 @@ u32 sd_get_mode()
int sd_init_retry(bool power_cycle)
{
u32 bus_width = SDMMC_BUS_WIDTH_4;
#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT
u32 type = SDHCI_TIMING_UHS_SDR104;
#else
u32 type = SDHCI_TIMING_UHS_DDR200;
#endif
// Power cycle SD card.
if (power_cycle)
@@ -92,24 +104,45 @@ int sd_init_retry(bool power_cycle)
{
case SD_INIT_FAIL: // Reset to max.
return 0;
case SD_1BIT_HS25:
bus_width = SDMMC_BUS_WIDTH_1;
type = SDHCI_TIMING_SD_HS25;
break;
case SD_4BIT_HS25:
type = SDHCI_TIMING_SD_HS25;
break;
case SD_UHS_SDR82:
type = SDHCI_TIMING_UHS_SDR82;
break;
case SD_UHS_SDR104:
type = SDHCI_TIMING_UHS_SDR104;
break;
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
case SD_UHS_DDR208:
type = SDHCI_TIMING_UHS_DDR200;
break;
#endif
default:
sd_mode = SD_UHS_SDR104;
sd_mode = SD_DEFAULT_SPEED;
break;
}
return sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type);
int res = sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type);
if (res)
{
sd_init_done = true;
insertion_event = true;
}
else
sd_init_done = false;
return res;
}
bool sd_initialize(bool power_cycle)
@@ -125,7 +158,7 @@ bool sd_initialize(bool power_cycle)
return true;
else if (!sdmmc_get_sd_inserted()) // SD Card is not inserted.
{
sd_mode = SD_UHS_SDR104;
sd_mode = SD_DEFAULT_SPEED;
break;
}
else
@@ -146,7 +179,7 @@ bool sd_initialize(bool power_cycle)
bool sd_mount()
{
if (sd_mounted)
if (sd_init_done && sd_mounted)
return true;
int res = 0;
@@ -165,8 +198,8 @@ bool sd_mount()
}
else
{
sd_init_done = true;
res = f_mount(&sd_fs, "0:", 1); // Volume 0 is SD.
if (!sd_mounted)
res = f_mount(&sd_fs, "0:", 1); // Volume 0 is SD.
if (res == FR_OK)
{
sd_mounted = true;
@@ -184,19 +217,25 @@ bool sd_mount()
static void _sd_deinit(bool deinit)
{
if (deinit && sd_mode == SD_INIT_FAIL)
sd_mode = SD_UHS_SDR104;
if (deinit)
{
insertion_event = false;
if (sd_mode == SD_INIT_FAIL)
sd_mode = SD_DEFAULT_SPEED;
}
if (sd_init_done && sd_mounted)
if (sd_init_done)
{
f_mount(NULL, "0:", 1); // Volume 0 is SD.
sd_mounted = false;
}
if (sd_init_done && deinit)
{
sdmmc_storage_end(&sd_storage);
sd_init_done = false;
if (sd_mounted)
f_mount(NULL, "0:", 1); // Volume 0 is SD.
if (deinit)
{
sdmmc_storage_end(&sd_storage);
sd_init_done = false;
}
}
sd_mounted = false;
}
void sd_unmount() { _sd_deinit(false); }
@@ -210,6 +249,9 @@ bool sd_is_gpt()
void *sd_file_read(const char *path, u32 *fsize)
{
FIL fp;
if (!sd_get_card_mounted())
return NULL;
if (f_open(&fp, path, FA_READ) != FR_OK)
return NULL;
@@ -237,6 +279,9 @@ int sd_save_to_file(void *buf, u32 size, const char *filename)
{
FIL fp;
u32 res = 0;
if (!sd_get_card_mounted())
return FR_DISK_ERR;
res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE);
if (res)
{

10
bdk/storage/sd.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2021 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -22,13 +22,19 @@
#include <storage/sdmmc_driver.h>
#include <libs/fatfs/ff.h>
#define SD_BLOCKSIZE 512
enum
{
SD_INIT_FAIL = 0,
SD_1BIT_HS25 = 1,
SD_4BIT_HS25 = 2,
SD_UHS_SDR82 = 3,
SD_UHS_SDR104 = 4
SD_UHS_SDR104 = 4,
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
SD_UHS_DDR208 = 5
#endif
};
enum

92
bdk/storage/sd_def.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved.
* Copyright (c) 2018-2021 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -45,15 +45,14 @@
#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */
/* OCR bit definitions */
#define SD_OCR_VDD_18 (1 << 7) /* VDD voltage 1.8 */
#define SD_VHD_27_36 (1 << 8) /* VDD voltage 2.7 ~ 3.6 */
#define SD_OCR_VDD_27_34 (0x7F << 15) /* VDD voltage 2.7 ~ 3.4 */
#define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
#define SD_OCR_XPC (1 << 28) /* SDXC power control */
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
#define SD_OCR_BUSY (1 << 31) /* Card Power up Status */
#define SD_OCR_VDD_18 (1U << 7) /* VDD voltage 1.8 */
#define SD_VHD_27_36 (1U << 8) /* VDD voltage 2.7 ~ 3.6 */
#define SD_OCR_VDD_32_33 (1U << 20) /* VDD voltage 3.2 ~ 3.3 */
#define SD_OCR_S18R (1U << 24) /* 1.8V switching request */
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
#define SD_OCR_XPC (1U << 28) /* SDXC power control */
#define SD_OCR_CCS (1U << 30) /* Card Capacity Status */
#define SD_OCR_BUSY (1U << 31) /* Card Power up Status */
/*
* SD_SWITCH argument format:
@@ -90,8 +89,8 @@
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
#define SD_SCR_BUS_WIDTH_1 (1<<0)
#define SD_SCR_BUS_WIDTH_4 (1<<2)
#define SD_SCR_BUS_WIDTH_1 (1U << 0)
#define SD_SCR_BUS_WIDTH_4 (1U << 2)
/*
* SD bus widths
@@ -102,33 +101,55 @@
/*
* SD bus speeds
*/
#define UHS_SDR12_BUS_SPEED 0
#define UHS_SDR12_BUS_SPEED 0
#define HIGH_SPEED_BUS_SPEED 1
#define UHS_SDR25_BUS_SPEED 1
#define UHS_SDR50_BUS_SPEED 2
#define UHS_SDR25_BUS_SPEED 1
#define UHS_SDR50_BUS_SPEED 2
#define UHS_SDR104_BUS_SPEED 3
#define UHS_DDR50_BUS_SPEED 4
#define HS400_BUS_SPEED 5
#define UHS_DDR50_BUS_SPEED 4
#define HS400_BUS_SPEED 5
#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED)
#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
#define SD_MODE_HIGH_SPEED (1U << HIGH_SPEED_BUS_SPEED)
#define SD_MODE_UHS_SDR12 (1U << UHS_SDR12_BUS_SPEED)
#define SD_MODE_UHS_SDR25 (1U << UHS_SDR25_BUS_SPEED)
#define SD_MODE_UHS_SDR50 (1U << UHS_SDR50_BUS_SPEED)
#define SD_MODE_UHS_SDR104 (1U << UHS_SDR104_BUS_SPEED)
#define SD_MODE_UHS_DDR50 (1U << UHS_DDR50_BUS_SPEED)
#define SD_DRIVER_TYPE_B 0x01
#define SD_DRIVER_TYPE_A 0x02
#define SD_SET_CURRENT_LIMIT_200 0
#define SD_SET_CURRENT_LIMIT_400 1
#define SD_SET_CURRENT_LIMIT_600 2
#define SD_SET_CURRENT_LIMIT_800 3
#define SD_SET_DRIVER_TYPE_B 0
#define SD_SET_DRIVER_TYPE_A 1
#define SD_SET_DRIVER_TYPE_C 2
#define SD_SET_DRIVER_TYPE_D 3
#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
#define SD_DRIVER_TYPE_B (1U << SD_SET_DRIVER_TYPE_B)
#define SD_DRIVER_TYPE_A (1U << SD_SET_DRIVER_TYPE_A)
#define SD_DRIVER_TYPE_C (1U << SD_SET_DRIVER_TYPE_C)
#define SD_DRIVER_TYPE_D (1U << SD_SET_DRIVER_TYPE_D)
#define SD_SET_POWER_LIMIT_0_72 0
#define SD_SET_POWER_LIMIT_1_44 1
#define SD_SET_POWER_LIMIT_2_16 2
#define SD_SET_POWER_LIMIT_2_88 3
#define SD_MAX_POWER_0_72 (1U << SD_SET_POWER_LIMIT_0_72)
#define SD_MAX_POWER_1_44 (1U << SD_SET_POWER_LIMIT_1_44)
#define SD_MAX_POWER_2_16 (1U << SD_SET_POWER_LIMIT_2_16)
#define SD_MAX_POWER_2_88 (1U << SD_SET_POWER_LIMIT_2_88)
#define SD_SET_CMD_SYSTEM_DEF 0
#define SD_SET_CMD_SYSTEM_MEC 1
#define SD_SET_CMD_SYSTEM_OTP 3
#define SD_SET_CMD_SYSTEM_OSD 3
#define SD_SET_CMD_SYSTEM_VND 14
#define UHS_DDR200_BUS_SPEED SD_SET_CMD_SYSTEM_VND
#define SD_CMD_SYSTEM_DEF (1U << SD_SET_CMD_SYSTEM_DEF)
#define SD_CMD_SYSTEM_MEC (1U << SD_SET_CMD_SYSTEM_MEC)
#define SD_CMD_SYSTEM_OTP (1U << SD_SET_CMD_SYSTEM_OTP)
#define SD_CMD_SYSTEM_OSD (1U << SD_SET_CMD_SYSTEM_OSD)
#define SD_CMD_SYSTEM_VND (1U << SD_SET_CMD_SYSTEM_VND)
#define SD_MODE_UHS_DDR200 SD_CMD_SYSTEM_VND
/*
* SD_SWITCH mode
@@ -140,11 +161,14 @@
* SD_SWITCH function groups
*/
#define SD_SWITCH_GRP_ACCESS 0
#define SD_SWITCH_GRP_CMDSYS 1
#define SD_SWITCH_GRP_DRVSTR 2
#define SD_SWITCH_GRP_PWRLIM 3
/*
* SD_SWITCH access modes
*/
#define SD_SWITCH_ACCESS_DEF 0
#define SD_SWITCH_ACCESS_HS 1
#define SD_SWITCH_ACCESS_HS 1
#endif /* SD_DEF_H */

746
bdk/storage/sdmmc.c
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File diff suppressed because it is too large Load Diff

9
bdk/storage/sdmmc.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2021 CTCaer
* Copyright (c) 2018-2022 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -129,10 +129,7 @@ typedef struct _mmc_csd
u16 cmdclass;
u32 c_size;
u32 r2w_factor;
u32 max_dtr;
u32 erase_size; /* In sectors */
u32 read_blkbits;
u32 write_blkbits;
u32 capacity;
u8 write_protect;
u16 busspeed;
@@ -186,6 +183,7 @@ typedef struct _sdmmc_storage_t
int is_low_voltage;
u32 partition;
int initialized;
u32 card_power_limit;
u8 raw_cid[0x10];
u8 raw_csd[0x10];
u8 raw_scr[8];
@@ -209,6 +207,9 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg);
int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf);
int mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf);
int sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf);
int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf);
u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage);

438
bdk/storage/sdmmc_driver.c
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2022 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -27,16 +27,15 @@
#include <soc/hw_init.h>
#include <soc/pinmux.h>
#include <soc/pmc.h>
#include <soc/timer.h>
#include <soc/t210.h>
#include <utils/util.h>
//#define DPRINTF(...) gfx_printf(__VA_ARGS__)
//#define ERROR_EXTRA_PRINTING
#define DPRINTF(...)
#ifdef BDK_SDMMC_OC_AND_EXTRA_PRINT
#ifdef BDK_SDMMC_EXTRA_PRINT
#define ERROR_EXTRA_PRINTING
#define SDMMC_EMMC_OC
#endif
/*! SCMMC controller base addresses. */
@@ -88,9 +87,9 @@ static int _sdmmc_set_io_power(sdmmc_t *sdmmc, u32 power)
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc)
{
u32 h = sdmmc->regs->hostctl;
if (h & SDHCI_CTRL_8BITBUS)
if (h & SDHCI_CTRL_8BITBUS) // eMMC only (or UHS-II).
return SDMMC_BUS_WIDTH_8;
if (h & SDHCI_CTRL_4BITBUS)
if (h & SDHCI_CTRL_4BITBUS) // SD only.
return SDMMC_BUS_WIDTH_4;
return SDMMC_BUS_WIDTH_1;
}
@@ -102,28 +101,28 @@ void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width)
if (bus_width == SDMMC_BUS_WIDTH_1)
sdmmc->regs->hostctl = host_control;
else if (bus_width == SDMMC_BUS_WIDTH_4)
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS;
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS; // SD only.
else if (bus_width == SDMMC_BUS_WIDTH_8)
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS;
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS; // eMMC only (or UHS-II).
}
void sdmmc_save_tap_value(sdmmc_t *sdmmc)
{
sdmmc->venclkctl_tap = sdmmc->regs->venclkctl >> 16;
sdmmc->venclkctl_tap = (sdmmc->regs->venclkctl & 0xFF0000) >> 16;
sdmmc->venclkctl_set = 1;
}
static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
{
const u32 dqs_trim_val = 0x28;
const u32 tap_values_t210[] = { 4, 0, 3, 0 };
const u32 dqs_trim_val = 40; // 24 if HS533/HS667.
const u8 tap_values_t210[4] = { 4, 0, 3, 0 };
u32 tap_val = 0;
if (type == SDHCI_TIMING_MMC_HS400)
sdmmc->regs->vencapover = (sdmmc->regs->vencapover & 0xFFFFC0FF) | (dqs_trim_val << 8);
sdmmc->regs->ventunctl0 &= ~TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW;
sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
if (type == SDHCI_TIMING_MMC_HS400)
{
@@ -140,9 +139,9 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
return 1;
}
static int _sdmmc_commit_changes(sdmmc_t *sdmmc)
static void _sdmmc_commit_changes(sdmmc_t *sdmmc)
{
return sdmmc->regs->clkcon;
(void)sdmmc->regs->clkcon;
}
static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power)
@@ -173,8 +172,8 @@ static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power)
break;
case SDMMC_4: // 50 Ohm 2X Driver. PU:16, PD:16, B01: PU:10, PD:10.
APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) =
(APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | (sdmmc->t210b01 ? 0xA28 : 0x1040);
APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) |
(sdmmc->t210b01 ? 0xA28 : 0x1040);
(void)APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL); // Commit write.
break;
}
@@ -189,21 +188,21 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
}
// Enable E_INPUT power.
if (!(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD))
// Enable E_INPUT (SD) or Disable E_PWRD (eMMC) power.
if (!(sdmmc->regs->sdmemcmppadctl & SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD))
{
sdmmc->regs->sdmemcmppadctl |= TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD;
sdmmc->regs->sdmemcmppadctl |= SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD;
_sdmmc_commit_changes(sdmmc);
usleep(1);
}
// Enable auto calibration and start auto configuration.
sdmmc->regs->autocalcfg |= TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE | TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START;
sdmmc->regs->autocalcfg |= SDHCI_TEGRA_AUTOCAL_ENABLE | SDHCI_TEGRA_AUTOCAL_START;
_sdmmc_commit_changes(sdmmc);
usleep(2);
u32 timeout = get_tmr_ms() + 10;
while (sdmmc->regs->autocalsts & TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE)
while (sdmmc->regs->autocalsts & SDHCI_TEGRA_AUTOCAL_ACTIVE)
{
if (get_tmr_ms() > timeout)
{
@@ -215,33 +214,29 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
#ifdef ERROR_EXTRA_PRINTING
// Check if Comp pad is open or short to ground.
// SDMMC1: CZ pads - T210/T210B01: 7-bit/5-bit. SDMMC2/4: LV_CZ pads - 5-bit.
u8 code_mask = (sdmmc->t210b01 || sdmmc->id != SDMMC_1) ? 0x1F : 0x7F;
u8 autocal_pu_status = sdmmc->regs->autocalsts & code_mask;
// Use 0x1F mask for all.
u8 autocal_pu_status = sdmmc->regs->autocalsts & 0x1F;
if (!autocal_pu_status)
EPRINTF("SDMMC: Comp Pad short to gnd!");
else if (autocal_pu_status == code_mask)
EPRINTF("SDMMC: Comp Pad open!");
EPRINTFARGS("SDMMC%d: Comp Pad open!", sdmmc->id + 1);
else if (autocal_pu_status == 0x1F)
EPRINTFARGS("SDMMC%d: Comp Pad short to gnd!", sdmmc->id + 1);
#endif
// In case auto calibration fails, we load suggested standard values.
if (!timeout)
{
sdmmc->regs->autocalcfg &= ~SDHCI_TEGRA_AUTOCAL_ENABLE;
_sdmmc_pad_config_fallback(sdmmc, power);
sdmmc->regs->autocalcfg &= ~TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE;
}
// Disable E_INPUT to conserve power.
sdmmc->regs->sdmemcmppadctl &= ~TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD;
// Disable E_INPUT (SD) or enable E_PWRD (eMMC) to conserve power.
sdmmc->regs->sdmemcmppadctl &= ~SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD;
if(should_enable_sd_clock)
if (should_enable_sd_clock)
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
}
#ifdef SDMMC_EMMC_OC
static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc, bool overclock)
#else
static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
#endif
{
int result = 1, should_disable_sd_clock = 0;
@@ -251,17 +246,15 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
}
#ifdef SDMMC_EMMC_OC
// Add -4 TX_DLY_CODE_OFFSET if HS533.
if (sdmmc->id == SDMMC_4 && overclock)
sdmmc->regs->vendllcalcfg = sdmmc->regs->vendllcalcfg &= 0xFFFFC07F | (0x7C << 7);
#endif
// Add -4 TX_DLY_CODE_OFFSET if HS533/HS667.
// if (sdmmc->id == SDMMC_4 && sdmmc->card_clock > 208000)
// sdmmc->regs->vendllctl0 = sdmmc->regs->vendllctl0 &= 0xFFFFC07F | (0x7C << 7);
sdmmc->regs->vendllcalcfg |= TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE;
sdmmc->regs->vendllcalcfg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
_sdmmc_commit_changes(sdmmc);
u32 timeout = get_tmr_ms() + 5;
while (sdmmc->regs->vendllcalcfg & TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE)
while (sdmmc->regs->vendllcalcfg & SDHCI_TEGRA_DLLCAL_CALIBRATE)
{
if (get_tmr_ms() > timeout)
{
@@ -271,7 +264,7 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
}
timeout = get_tmr_ms() + 10;
while (sdmmc->regs->vendllcalcfgsts & TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE)
while (sdmmc->regs->vendllcalcfgsts & SDHCI_TEGRA_DLLCAL_ACTIVE)
{
if (get_tmr_ms() > timeout)
{
@@ -286,7 +279,7 @@ out:;
return result;
}
static void _sdmmc_reset(sdmmc_t *sdmmc)
static void _sdmmc_reset_cmd_data(sdmmc_t *sdmmc)
{
sdmmc->regs->swrst |= SDHCI_RESET_CMD | SDHCI_RESET_DATA;
_sdmmc_commit_changes(sdmmc);
@@ -304,6 +297,13 @@ static void _sdmmc_reset_all(sdmmc_t *sdmmc)
;
}
void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type)
{
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_DRV_TYPE_MASK)) | SDHCI_CTRL_DRV_TYPE(type);
_sdmmc_commit_changes(sdmmc);
}
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
{
// Disable the SD clock if it was enabled, and reenable it later.
@@ -316,7 +316,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
_sdmmc_config_tap_val(sdmmc, type);
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
switch (type)
{
@@ -335,28 +335,35 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
break;
case SDHCI_TIMING_MMC_HS200:
case SDHCI_TIMING_UHS_SDR50: // T210 Errata for SDR50, the host must be set to SDR104.
case SDHCI_TIMING_UHS_SDR50: // T210 Errata: the host must be set to SDR104 to WAR a CRC issue.
case SDHCI_TIMING_UHS_SDR104:
case SDHCI_TIMING_UHS_SDR82:
case SDHCI_TIMING_UHS_DDR50:
case SDHCI_TIMING_MMC_HS102:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
case SDHCI_TIMING_MMC_HS100:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
case SDHCI_TIMING_MMC_HS400:
// Non standard.
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED;
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | HS400_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
case SDHCI_TIMING_UHS_SDR25:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR25_BUS_SPEED;
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR25_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
case SDHCI_TIMING_UHS_SDR12:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR12_BUS_SPEED;
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR12_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
case SDHCI_TIMING_UHS_DDR50:
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
case SDHCI_TIMING_UHS_DDR200:
#endif
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_DDR50_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
}
@@ -367,31 +374,22 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
u16 divisor;
clock_sdmmc_get_card_clock_div(&clock, &divisor, type);
clock_sdmmc_config_clock_source(&clock, sdmmc->id, clock);
sdmmc->divisor = (clock + divisor - 1) / divisor;
sdmmc->card_clock = (clock + divisor - 1) / divisor;
//if divisor != 1 && divisor << 31 -> error
// (divisor != 1) && (divisor & 1) -> error
u16 div = divisor >> 1;
divisor = 0;
if (div > 0xFF)
divisor = div >> SDHCI_DIVIDER_SHIFT;
u16 div_lo = divisor >> 1;
u16 div_hi = div_lo >> 8;
sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK))
| (div << SDHCI_DIVIDER_SHIFT) | (divisor << SDHCI_DIVIDER_HI_SHIFT);
sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK)) |
(div_lo << SDHCI_DIV_LO_SHIFT) | (div_hi << SDHCI_DIV_HI_SHIFT);
// Enable the SD clock again.
if (should_enable_sd_clock)
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
if (type == SDHCI_TIMING_MMC_HS400)
{
#ifdef SDMMC_EMMC_OC
bool overclock_en = clock > 208000;
return _sdmmc_dll_cal_execute(sdmmc, overclock_en);
#else
return _sdmmc_dll_cal_execute(sdmmc);
#endif
}
return 1;
}
@@ -521,10 +519,10 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
_sdmmc_commit_changes(sdmmc);
u32 timeout = get_tmr_ms() + 2000;
while(sdmmc->regs->prnsts & SDHCI_CMD_INHIBIT)
while (sdmmc->regs->prnsts & SDHCI_CMD_INHIBIT)
if (get_tmr_ms() > timeout)
{
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
@@ -534,7 +532,7 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
while (sdmmc->regs->prnsts & SDHCI_DATA_INHIBIT)
if (get_tmr_ms() > timeout)
{
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
}
@@ -547,10 +545,10 @@ static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc)
_sdmmc_commit_changes(sdmmc);
u32 timeout = get_tmr_ms() + 2000;
while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL_MASK))
while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL))
if (get_tmr_ms() > timeout)
{
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
@@ -594,7 +592,7 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_presen
if (cmd->check_busy)
cmdflags = SDHCI_CMD_RESP_LEN48_BUSY | SDHCI_CMD_INDEX | SDHCI_CMD_CRC;
else
cmdflags = SDHCI_CMD_RESP_LEN48 | SDHCI_CMD_INDEX | SDHCI_CMD_CRC;
cmdflags = SDHCI_CMD_RESP_LEN48 | SDHCI_CMD_INDEX | SDHCI_CMD_CRC;
break;
case SDMMC_RSP_TYPE_2:
@@ -611,8 +609,9 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_presen
if (is_data_present)
cmdflags |= SDHCI_CMD_DATA;
sdmmc->regs->argument = cmd->arg;
sdmmc->regs->cmdreg = (cmd->cmd << 8) | cmdflags;
sdmmc->regs->cmdreg = SDHCI_CMD_IDX(cmd->cmd) | cmdflags;
return 1;
}
@@ -627,10 +626,8 @@ static void _sdmmc_send_tuning_cmd(sdmmc_t *sdmmc, u32 cmd)
_sdmmc_send_cmd(sdmmc, &cmdbuf, true);
}
static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
{
if (sdmmc->powersave_enabled)
return 0;
if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, true))
return 0;
@@ -640,11 +637,21 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
sdmmc->regs->norintsts = sdmmc->regs->norintsts;
sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
// Set tap if manual tuning.
if (tap != HW_TAP_TUNING)
{
sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (tap << 16);
sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
}
#endif
_sdmmc_send_tuning_cmd(sdmmc, cmd);
_sdmmc_commit_changes(sdmmc);
usleep(1);
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
_sdmmc_commit_changes(sdmmc);
@@ -657,59 +664,170 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
sdmmc->regs->norintsts = SDHCI_INT_DATA_AVAIL;
sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL;
_sdmmc_commit_changes(sdmmc);
usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
return 1;
}
}
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL;
_sdmmc_commit_changes(sdmmc);
usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
return 0;
}
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
typedef struct _sdmmc_manual_tuning_t
{
u32 result[8];
u32 num_iter;
u32 tap_start;
u32 tap_end;
} sdmmc_manual_tuning_t;
static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *tuning)
{
u32 tap_start = INVALID_TAP;
u32 win_size = 0;
u32 best_tap = 0;
u32 best_size = 0;
for (u32 i = 0; i < tuning->num_iter; i++)
{
u32 iter_end = i == (tuning->num_iter - 1) ? 1 : 0;
u32 stable = tuning->result[i / 32] & BIT(i % 32);
if (stable && !iter_end)
{
if (tap_start == INVALID_TAP)
tap_start = i;
win_size++;
}
else
{
if (tap_start != INVALID_TAP)
{
u32 tap_end = !iter_end ? (i - 1) : i;
// Check if window is wider.
if (win_size > best_size)
{
best_tap = (tap_start + tap_end) / 2;
best_size = win_size + iter_end;
}
tap_start = INVALID_TAP;
win_size = 0;
}
}
}
// Check if failed or window too small.
if (!best_tap || best_size < SAMPLING_WINDOW_SIZE_MIN)
return 0;
sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
// Set tap.
sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (best_tap << 16);
sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
return 1;
}
/*
* SD Card DDR200 (DDR208) support
*
* On Tegra X1, that can be done with DDR50 host mode.
* That's because HS400 4-bit or HS400 generally, is not supported on SDMMC1/3.
* And also, tuning can't be done automatically on any DDR mode.
* So it needs to be done manually and selected tap will be applied from the biggest
* sampling window.
* That allows DDR200 support on every DDR200 sd card, other than the original maker
* of DDR200, Sandisk. Since Sandisk cards mandate DLL syncing.
*/
static int sdmmc_tuning_execute_ddr200(sdmmc_t *sdmmc)
{
sdmmc_manual_tuning_t manual_tuning = { 0 };
manual_tuning.num_iter = 128;
sdmmc->regs->ventunctl1 = 0; // step_size 1.
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | (2 << 13); // 128 Tries.
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier.
sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING;
for (u32 i = 0; i < manual_tuning.num_iter; i++)
{
_sdmmc_tuning_execute_once(sdmmc, MMC_SEND_TUNING_BLOCK, i);
// Save result for manual tuning.
int sampled = (sdmmc->regs->hostctl2 >> SDHCI_CTRL_TUNED_CLK_SHIFT) & 1;
manual_tuning.result[i / 32] |= sampled << (i % 32);
if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
break;
}
return _sdmmc_manual_tuning_set_tap(sdmmc, &manual_tuning);
}
#endif
int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
{
u32 max = 0, flag = 0;
u32 num_iter, flag;
if (sdmmc->powersave_enabled)
return 0;
switch (type)
{
case SDHCI_TIMING_MMC_HS200:
case SDHCI_TIMING_MMC_HS400:
case SDHCI_TIMING_UHS_SDR104:
case SDHCI_TIMING_UHS_SDR82:
max = 128;
num_iter = 128;
flag = (2 << 13); // 128 iterations.
break;
case SDHCI_TIMING_UHS_SDR50:
case SDHCI_TIMING_UHS_DDR50:
case SDHCI_TIMING_MMC_HS102:
max = 256;
case SDHCI_TIMING_UHS_DDR50: // HW tuning is not supported on DDR modes. But it sets tap to 0 which is proper.
case SDHCI_TIMING_MMC_HS100:
num_iter = 256;
flag = (4 << 13); // 256 iterations.
break;
case SDHCI_TIMING_MMC_HS400:
case SDHCI_TIMING_UHS_SDR12:
case SDHCI_TIMING_UHS_SDR25:
return 1;
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
case SDHCI_TIMING_UHS_DDR200:
return sdmmc_tuning_execute_ddr200(sdmmc);
#endif
default:
return 0;
}
sdmmc->regs->ventunctl1 = 0; // step_size 1.
sdmmc->regs->ventunctl1 = 0; // step_size 1.
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries.
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier.
sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries.
sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier.
sdmmc->regs->ventunctl0 |= TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING;
for (u32 i = 0; i < max; i++)
for (u32 i = 0; i < num_iter; i++)
{
_sdmmc_tuning_execute_once(sdmmc, cmd);
_sdmmc_tuning_execute_once(sdmmc, cmd, HW_TAP_TUNING);
if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
break;
}
@@ -734,14 +852,15 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN;
sdmmc->regs->clkcon &= ~SDHCI_PROG_CLOCK_MODE;
// Enable 32/64bit addressing if used (sysad. if blkcnt it fallbacks to 16bit).
sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;
if (!(sdmmc->regs->capareg & SDHCI_CAN_64BIT))
if (!(sdmmc->regs->capareg & SDHCI_CAP_64BIT))
return 0;
sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK;
sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE;
sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK; // Use SDMA. Host V4 enabled so adma address regs in use.
sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 14; // TMCLK * 2^27.
return 1;
}
@@ -766,8 +885,8 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
{
if (!sdmmc->t210b01)
{
off_pd = 123;
off_pu = 123;
off_pd = 0x7B; // -5.
off_pu = 0x7B; // -5.
}
else
{
@@ -779,7 +898,7 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
{
if (!sdmmc->t210b01)
{
off_pd = 125;
off_pd = 0x7D; // -3.
off_pu = 0;
}
}
@@ -806,12 +925,12 @@ static void _sdmmc_mask_interrupts(sdmmc_t *sdmmc)
sdmmc->regs->norintstsen &= ~(SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
}
static int _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
{
u16 norintsts = sdmmc->regs->norintsts;
u16 errintsts = sdmmc->regs->errintsts;
DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
if (pout)
*pout = norintsts;
@@ -820,7 +939,7 @@ DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
if (norintsts & SDHCI_INT_ERROR)
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTFARGS("SDMMC: norintsts %08X, errintsts %08X\n", norintsts, errintsts);
EPRINTFARGS("SDMMC%d: norintsts %08X, errintsts %08X\n", sdmmc->id + 1, norintsts, errintsts);
#endif
sdmmc->regs->errintsts = errintsts;
return SDMMC_MASKINT_ERROR;
@@ -841,12 +960,12 @@ static int _sdmmc_wait_response(sdmmc_t *sdmmc)
u32 timeout = get_tmr_ms() + 2000;
while (true)
{
int result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE);
u32 result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE);
if (result == SDMMC_MASKINT_MASKED)
break;
if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout)
{
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
}
@@ -896,11 +1015,11 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
should_disable_sd_clock = true;
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
_sdmmc_commit_changes(sdmmc);
usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
}
int result = _sdmmc_stop_transmission_inner(sdmmc, rsp);
usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
if (should_disable_sd_clock)
sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
@@ -908,7 +1027,7 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
return result;
}
static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
static int _sdmmc_config_sdma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
{
if (!req->blksize || !req->num_sectors)
return 0;
@@ -925,19 +1044,19 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
sdmmc->regs->admaaddr = admaaddr;
sdmmc->regs->admaaddr_hi = 0;
sdmmc->dma_addr_next = (admaaddr + 0x80000) & 0xFFF80000;
sdmmc->dma_addr_next = ALIGN_DOWN((admaaddr + SZ_512K), SZ_512K);
sdmmc->regs->blksize = req->blksize | 0x7000; // DMA 512KB (Detects A18 carry out).
sdmmc->regs->blkcnt = blkcnt;
sdmmc->regs->blksize = req->blksize | (7u << 12); // SDMA DMA 512KB Boundary (Detects A18 carry out).
sdmmc->regs->blkcnt = blkcnt;
if (blkcnt_out)
*blkcnt_out = blkcnt;
u32 trnmode = SDHCI_TRNS_DMA;
u32 trnmode = SDHCI_TRNS_DMA | SDHCI_TRNS_RTYPE_R1;
// Set mulitblock request.
// Set multiblock request.
if (req->is_multi_block)
trnmode = SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DMA;
trnmode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
// Set request direction.
if (!req->is_write)
@@ -954,7 +1073,7 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
return 1;
}
static int _sdmmc_update_dma(sdmmc_t *sdmmc)
static int _sdmmc_update_sdma(sdmmc_t *sdmmc)
{
u16 blkcnt = 0;
do
@@ -963,13 +1082,13 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
u32 timeout = get_tmr_ms() + 1500;
do
{
int result = 0;
u32 result = SDMMC_MASKINT_MASKED;
while (true)
{
u16 intr = 0;
result = _sdmmc_check_mask_interrupt(sdmmc, &intr,
SDHCI_INT_DATA_END | SDHCI_INT_DMA_END);
if (result < 0)
if (result != SDMMC_MASKINT_MASKED)
break;
if (intr & SDHCI_INT_DATA_END)
@@ -980,21 +1099,24 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
// Update DMA.
sdmmc->regs->admaaddr = sdmmc->dma_addr_next;
sdmmc->regs->admaaddr_hi = 0;
sdmmc->dma_addr_next += 0x80000;
sdmmc->dma_addr_next += SZ_512K;
}
}
if (result != SDMMC_MASKINT_NOERROR)
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTFARGS("%08X!", result);
EPRINTFARGS("SDMMC%d: int error!", sdmmc->id + 1);
#endif
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
} while (get_tmr_ms() < timeout);
} while (sdmmc->regs->blkcnt != blkcnt);
_sdmmc_reset(sdmmc);
_sdmmc_reset_cmd_data(sdmmc);
return 0;
}
@@ -1008,16 +1130,16 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
bool is_data_present = false;
if (req)
{
if (!_sdmmc_config_dma(sdmmc, &blkcnt, req))
if (!_sdmmc_config_sdma(sdmmc, &blkcnt, req))
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTF("SDMMC: DMA Wrong cfg!");
EPRINTFARGS("SDMMC%d: DMA Wrong cfg!", sdmmc->id + 1);
#endif
return 0;
}
// Flush cache before starting the transfer.
bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false);
is_data_present = true;
}
@@ -1027,7 +1149,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
if (!_sdmmc_send_cmd(sdmmc, cmd, is_data_present))
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTFARGS("SDMMC: Wrong Response type %08X!", cmd->rsp_type);
EPRINTFARGS("SDMMC%d: Wrong Response type %08X!", sdmmc->id + 1, cmd->rsp_type);
#endif
return 0;
}
@@ -1035,9 +1157,9 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
int result = _sdmmc_wait_response(sdmmc);
#ifdef ERROR_EXTRA_PRINTING
if (!result)
EPRINTF("SDMMC: Transfer timeout!");
EPRINTFARGS("SDMMC%d: Transfer timeout!", sdmmc->id + 1);
#endif
DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
sdmmc->regs->rspreg0, sdmmc->regs->rspreg1, sdmmc->regs->rspreg2, sdmmc->regs->rspreg3);
if (result)
{
@@ -1047,15 +1169,15 @@ DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
result = _sdmmc_cache_rsp(sdmmc, sdmmc->rsp, 0x10, cmd->rsp_type);
#ifdef ERROR_EXTRA_PRINTING
if (!result)
EPRINTF("SDMMC: Unknown response type!");
EPRINTFARGS("SDMMC%d: Unknown response type!", sdmmc->id + 1);
#endif
}
if (req && result)
{
result = _sdmmc_update_dma(sdmmc);
result = _sdmmc_update_sdma(sdmmc);
#ifdef ERROR_EXTRA_PRINTING
if (!result)
EPRINTF("SDMMC: DMA Update failed!");
EPRINTFARGS("SDMMC%d: DMA Update failed!", sdmmc->id + 1);
#endif
}
}
@@ -1066,8 +1188,8 @@ DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
{
if (req)
{
// Flush cache after transfer.
bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
// Invalidate cache after transfer.
bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
if (blkcnt_out)
*blkcnt_out = blkcnt;
@@ -1081,7 +1203,7 @@ DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
result = _sdmmc_wait_card_busy(sdmmc);
#ifdef ERROR_EXTRA_PRINTING
if (!result)
EPRINTF("SDMMC: Busy timeout!");
EPRINTFARGS("SDMMC%d: Busy timeout!", sdmmc->id + 1);
#endif
return result;
}
@@ -1149,12 +1271,11 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
// Configure SD card detect.
PINMUX_AUX(PINMUX_AUX_GPIO_PZ1) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | 2; // GPIO control, pull up.
APB_MISC(APB_MISC_GP_VGPIO_GPIO_MUX_SEL) = 0;
gpio_config(GPIO_PORT_Z, GPIO_PIN_1, GPIO_MODE_GPIO);
gpio_output_enable(GPIO_PORT_Z, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
gpio_direction_input(GPIO_PORT_Z, GPIO_PIN_1);
usleep(100);
// Check if SD card is inserted.
if(!sdmmc_get_sd_inserted())
if (!sdmmc_get_sd_inserted())
return 0;
/*
@@ -1170,6 +1291,7 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1;
// Configure SDMMC1 CLK pinmux, based on state and SoC type.
PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) &= ~PINMUX_SCHMT;
if (PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) != (PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN)) // Check if CLK pad is already configured.
PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | (t210b01 ? PINMUX_PULL_NONE : PINMUX_PULL_DOWN);
@@ -1185,20 +1307,20 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
_sdmmc_config_sdmmc1_schmitt();
// Make sure the SDMMC1 controller is powered.
PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1_IO_EN;
usleep(1000);
PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
// Set enable SD card power.
PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2;
gpio_direction_output(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH);
usleep(10000);
// Inform IO pads that voltage is gonna be 3.3V.
PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
// Set enable SD card power.
PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2; // Pull down.
gpio_config(GPIO_PORT_E, GPIO_PIN_4, GPIO_MODE_GPIO);
gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH);
gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
usleep(10000);
// Enable SD card IO power.
max7762x_regulator_set_voltage(REGULATOR_LDO2, 3300000);
max7762x_regulator_enable(REGULATOR_LDO2, true);
@@ -1235,7 +1357,7 @@ static void _sdmmc_config_emmc(u32 id, bool t210b01)
APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) &= 0xF8003FFF;
// Set default pad cfg.
if (t210b01)
APB_MISC(APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL) &= 0xFFBFFFF9; // Unset CMD/CLK/DQS powedown.
APB_MISC(APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL) &= 0xFFBFFFF9; // Unset CMD/CLK/DQS weak pull up/down.
// Enable schmitt trigger.
APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) |= 1;
(void)APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL); // Commit write.
@@ -1243,15 +1365,15 @@ static void _sdmmc_config_emmc(u32 id, bool t210b01)
}
}
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable)
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
{
u32 clock;
u16 divisor;
u8 vref_sel = 7;
const u32 trim_values_t210[] = { 2, 8, 3, 8 };
const u32 trim_values_t210b01[] = { 14, 13, 15, 13 };
const u32 *trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210;
const u8 trim_values_t210[4] = { 2, 8, 3, 8 };
const u8 trim_values_t210b01[4] = { 14, 13, 15, 13 };
const u8 *trim_values;
if (id > SDMMC_4 || id == SDMMC_3)
return 0;
@@ -1263,6 +1385,8 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
sdmmc->clock_stopped = 1;
sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01;
trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210;
// Do specific SDMMC HW configuration.
switch (id)
{
@@ -1298,11 +1422,10 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
sdmmc->clock_stopped = 0;
// Set default pad IO trimming configuration.
sdmmc->regs->iospare |= 0x80000; // Enable muxing.
sdmmc->regs->veniotrimctl &= 0xFFFFFFFB; // Set Band Gap VREG to supply DLL.
sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | (trim_values[sdmmc->id] << 24);
sdmmc->regs->sdmemcmppadctl =
(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK) | vref_sel;
sdmmc->regs->iospare |= BIT(19); // Enable 1 cycle delayed cmd_oen.
sdmmc->regs->veniotrimctl &= ~BIT(2); // Set Band Gap VREG to supply DLL.
sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | ((u32)trim_values[sdmmc->id] << 24);
sdmmc->regs->sdmemcmppadctl = (sdmmc->regs->sdmemcmppadctl & ~SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK) | vref_sel;
// Configure auto calibration values.
if (!_sdmmc_autocal_config_offset(sdmmc, power))
@@ -1319,7 +1442,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
if (sdmmc_setup_clock(sdmmc, type))
{
sdmmc_card_clock_powersave(sdmmc, powersave_enable);
sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_DISABLE);
_sdmmc_card_clock_enable(sdmmc);
_sdmmc_commit_changes(sdmmc);
@@ -1405,11 +1528,11 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
should_disable_sd_clock = 1;
sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
_sdmmc_commit_changes(sdmmc);
usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
}
int result = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out);
usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
if (should_disable_sd_clock)
sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
@@ -1419,10 +1542,7 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
{
if(sdmmc->id != SDMMC_1)
return 0;
if (!sdmmc_setup_clock(sdmmc, SDHCI_TIMING_UHS_SDR12))
if (sdmmc->id != SDMMC_1)
return 0;
_sdmmc_commit_changes(sdmmc);

314
bdk/storage/sdmmc_driver.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2019 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -22,21 +22,16 @@
#include <storage/sdmmc_t210.h>
/*! SDMMC controller IDs. */
#define SDMMC_1 0
#define SDMMC_2 1
#define SDMMC_3 2
#define SDMMC_4 3
#define SDMMC_1 0 // Version 4.00.
#define SDMMC_2 1 // Version 5.0 + SW CQE + Enhanced Strobe.
#define SDMMC_3 2 // Version 4.00.
#define SDMMC_4 3 // Version 5.0 + SW CQE + Enhanced Strobe.
/*! SDMMC power types. */
#define SDMMC_POWER_OFF 0
#define SDMMC_POWER_1_8 1
#define SDMMC_POWER_3_3 2
/*! SDMMC bus widths. */
#define SDMMC_BUS_WIDTH_1 0
#define SDMMC_BUS_WIDTH_4 1
#define SDMMC_BUS_WIDTH_8 2
/*! SDMMC response types. */
#define SDMMC_RSP_TYPE_0 0
#define SDMMC_RSP_TYPE_1 1
@@ -45,131 +40,203 @@
#define SDMMC_RSP_TYPE_4 4
#define SDMMC_RSP_TYPE_5 5
/*! SDMMC bus widths. */
#define SDMMC_BUS_WIDTH_1 0
#define SDMMC_BUS_WIDTH_4 1
#define SDMMC_BUS_WIDTH_8 2
/*! SDMMC mask interrupt status. */
#define SDMMC_MASKINT_MASKED 0
#define SDMMC_MASKINT_NOERROR -1
#define SDMMC_MASKINT_ERROR -2
#define SDMMC_MASKINT_NOERROR 1
#define SDMMC_MASKINT_ERROR 2
/*! SDMMC present state. */
#define SDHCI_CMD_INHIBIT 0x1
#define SDHCI_DATA_INHIBIT 0x2
#define SDHCI_DOING_WRITE 0x100
#define SDHCI_DOING_READ 0x200
#define SDHCI_SPACE_AVAILABLE 0x400
#define SDHCI_DATA_AVAILABLE 0x800
#define SDHCI_CARD_PRESENT 0x10000
#define SDHCI_CD_STABLE 0x20000
#define SDHCI_CD_LVL 0x40000
#define SDHCI_WRITE_PROTECT 0x80000
/*! SDMMC present state. 0x24. */
#define SDHCI_CMD_INHIBIT BIT(0)
#define SDHCI_DATA_INHIBIT BIT(1)
#define SDHCI_DAT_LINE_ACTIVE BIT(2)
#define SDHCI_RETUNING_REQUEST BIT(3)
#define SDHCI_EMMC_LINE_LVL_MASK (0xFU << 4)
#define SDHCI_DATA_4_LVL BIT(4) // eMMC only.
#define SDHCI_DATA_5_LVL BIT(5) // eMMC only.
#define SDHCI_DATA_6_LVL BIT(6) // eMMC only.
#define SDHCI_DATA_7_LVL BIT(7) // eMMC only.
#define SDHCI_DOING_WRITE BIT(8)
#define SDHCI_DOING_READ BIT(9) // SD only.
#define SDHCI_SPACE_AVAILABLE BIT(10) // Write buffer empty.
#define SDHCI_DATA_AVAILABLE BIT(11) // Read buffer has data.
#define SDHCI_CARD_PRESENT BIT(16)
#define SDHCI_CD_STABLE BIT(17)
#define SDHCI_CD_LVL BIT(18)
#define SDHCI_WRITE_PROTECT BIT(19)
#define SDHCI_DATA_LVL_MASK 0xF00000
#define SDHCI_DATA_0_LVL_MASK 0x100000
#define SDHCI_CMD_LVL 0x1000000
#define SDHCI_DATA_0_LVL BIT(20)
#define SDHCI_DATA_1_LVL BIT(21)
#define SDHCI_DATA_2_LVL BIT(22)
#define SDHCI_DATA_3_LVL BIT(23)
#define SDHCI_CMD_LVL BIT(24)
/*! SDMMC transfer mode. */
#define SDHCI_TRNS_DMA 0x01
#define SDHCI_TRNS_BLK_CNT_EN 0x02
#define SDHCI_TRNS_AUTO_CMD12 0x04
#define SDHCI_TRNS_AUTO_CMD23 0x08
#define SDHCI_TRNS_AUTO_SEL 0x0C
#define SDHCI_TRNS_WRITE 0x00
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
/*! SDMMC transfer mode. 0x0C. */
#define SDHCI_TRNS_DMA BIT(0)
#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
#define SDHCI_TRNS_AUTO_CMD12 (1U << 2)
#define SDHCI_TRNS_AUTO_CMD23 (2U << 2)
#define SDHCI_TRNS_WRITE (0U << 4)
#define SDHCI_TRNS_READ BIT(4)
#define SDHCI_TRNS_MULTI BIT(5)
#define SDHCI_TRNS_RTYPE_R1 (0U << 6)
#define SDHCI_TRNS_RTYPE_R5 BIT(6)
#define SDHCI_TRNS_RSP_ERR_CHK BIT(7)
#define SDHCI_TRNS_RSP_INT_DIS BIT(8)
/*! SDMMC command. */
/*! SDMMC command. 0x0E. */
#define SDHCI_CMD_RESP_MASK 0x3
#define SDHCI_CMD_RESP_NO_RESP 0x0
#define SDHCI_CMD_RESP_LEN136 0x1
#define SDHCI_CMD_RESP_LEN48 0x2
#define SDHCI_CMD_RESP_LEN48_BUSY 0x3
#define SDHCI_CMD_CRC 0x08
#define SDHCI_CMD_INDEX 0x10
#define SDHCI_CMD_DATA 0x20
#define SDHCI_CMD_ABORTCMD 0xC0
#define SDHCI_CMD_CRC BIT(3)
#define SDHCI_CMD_INDEX BIT(4)
#define SDHCI_CMD_DATA BIT(5)
#define SDHCI_CMD_TYPE_NORMAL (0U << 6)
#define SDHCI_CMD_TYPE_SUSPEND (1U << 6)
#define SDHCI_CMD_TYPE_RESUME (2U << 6)
#define SDHCI_CMD_TYPE_ABORT (3U << 6)
#define SDHCI_CMD_IDX(cmd) ((cmd) << 8)
/*! SDMMC host control. */
#define SDHCI_CTRL_LED 0x01
#define SDHCI_CTRL_4BITBUS 0x02
#define SDHCI_CTRL_HISPD 0x04
#define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_CTRL_CDTEST_INS 0x40
#define SDHCI_CTRL_CDTEST_EN 0x80
/*! SDMMC host control 2. */
#define SDHCI_CTRL_UHS_MASK 0xFFF8
#define SDHCI_CTRL_VDD_180 8
#define SDHCI_CTRL_DRV_TYPE_B 0x00
#define SDHCI_CTRL_DRV_TYPE_A 0x10
#define SDHCI_CTRL_DRV_TYPE_C 0x20
#define SDHCI_CTRL_DRV_TYPE_D 0x30
#define SDHCI_CTRL_EXEC_TUNING 0x40
#define SDHCI_CTRL_TUNED_CLK 0x80
#define SDHCI_HOST_VERSION_4_EN 0x1000
#define SDHCI_ADDRESSING_64BIT_EN 0x2000
#define SDHCI_CTRL_PRESET_VAL_EN 0x8000
/*! SDMMC host control. 0x28. */
#define SDHCI_CTRL_LED BIT(0)
#define SDHCI_CTRL_4BITBUS BIT(1) // SD only.
#define SDHCI_CTRL_HISPD BIT(2) // SD only.
#define SDHCI_CTRL_DMA_MASK (3U << 3)
#define SDHCI_CTRL_SDMA (0U << 3)
#define SDHCI_CTRL_ADMA1 (1U << 3)
#define SDHCI_CTRL_ADMA32 (2U << 3)
#define SDHCI_CTRL_ADMA64 (3U << 3)
#define SDHCI_CTRL_8BITBUS BIT(5) // eMMC only (or UHS-II).
#define SDHCI_CTRL_CDTEST_INS BIT(6)
#define SDHCI_CTRL_CDTEST_EN BIT(7)
/*! SDMMC power control. */
#define SDHCI_POWER_ON 0x01
#define SDHCI_POWER_180 0x0A
#define SDHCI_POWER_300 0x0C
#define SDHCI_POWER_330 0x0E
#define SDHCI_POWER_MASK 0xF1
/*! SDMMC host control 2. 0x3E. */
#define SDHCI_CTRL_UHS_MASK 0x7
#define SDHCI_CTRL_VDD_180 BIT(3)
#define SDHCI_CTRL_DRV_TYPE_MASK (3U << 4)
#define SDHCI_CTRL_DRV_TYPE_B (0U << 4)
#define SDHCI_CTRL_DRV_TYPE_A (1U << 4)
#define SDHCI_CTRL_DRV_TYPE_C (2U << 4)
#define SDHCI_CTRL_DRV_TYPE_D (3U << 4)
#define SDHCI_CTRL_DRV_TYPE(type) ((type) << 4)
#define SDHCI_CTRL_EXEC_TUNING BIT(6)
#define SDHCI_CTRL_TUNED_CLK_SHIFT 7
#define SDHCI_CTRL_TUNED_CLK BIT(7)
#define SDHCI_HOST_VERSION_4_EN BIT(12)
#define SDHCI_ADDRESSING_64BIT_EN BIT(13)
#define SDHCI_CTRL_PRESET_VAL_EN BIT(15)
// /*! SDMMC max current. */
// #define SDHCI_MAX_CURRENT_330_MASK 0xFF
// #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
// #define SDHCI_MAX_CURRENT_MULTIPLIER 4
/*! SDMMC power control. 0x29. */
#define SDHCI_POWER_ON BIT(0)
#define SDHCI_POWER_180 (5U << 1)
#define SDHCI_POWER_300 (6U << 1)
#define SDHCI_POWER_330 (7U << 1)
#define SDHCI_POWER_MASK 0xF1 // UHS-II only.
/*! SDMMC clock control. */
#define SDHCI_DIVIDER_SHIFT 8
#define SDHCI_DIVIDER_HI_SHIFT 6
#define SDHCI_DIV_MASK 0xFF00
#define SDHCI_DIV_HI_MASK 0xC0
#define SDHCI_PROG_CLOCK_MODE 0x20
#define SDHCI_CLOCK_CARD_EN 0x4
#define SDHCI_CLOCK_INT_STABLE 0x2
#define SDHCI_CLOCK_INT_EN 0x1
/*! SDMMC clock control. 0x2C. */
#define SDHCI_CLOCK_INT_EN BIT(0) // Internal Clock.
#define SDHCI_CLOCK_INT_STABLE BIT(1) // Internal Clock Stable.
#define SDHCI_CLOCK_CARD_EN BIT(2)
#define SDHCI_PROG_CLOCK_MODE BIT(5)
#define SDHCI_DIV_HI_SHIFT 6
#define SDHCI_DIV_HI_MASK (3U << SDHCI_DIV_HI_SHIFT)
#define SDHCI_DIV_LO_SHIFT 8
#define SDHCI_DIV_MASK (0xFFU << SDHCI_DIV_LO_SHIFT)
/*! SDMMC software reset. */
#define SDHCI_RESET_ALL 0x01
#define SDHCI_RESET_CMD 0x02
#define SDHCI_RESET_DATA 0x04
/*! SDMMC interrupt status and control. */
#define SDHCI_INT_RESPONSE 0x1
#define SDHCI_INT_DATA_END 0x2
#define SDHCI_INT_BLK_GAP 0x4
#define SDHCI_INT_DMA_END 0x8
#define SDHCI_INT_SPACE_AVAIL 0x10
#define SDHCI_INT_DATA_AVAIL 0x20
#define SDHCI_INT_CARD_INSERT 0x40
#define SDHCI_INT_CARD_REMOVE 0x80
#define SDHCI_INT_CARD_INT 0x100
#define SDHCI_INT_RETUNE 0x1000
#define SDHCI_INT_CQE 0x4000
#define SDHCI_INT_ERROR 0x8000
/*! SDMMC software reset. 0x2F. */
#define SDHCI_RESET_ALL BIT(0)
#define SDHCI_RESET_CMD BIT(1)
#define SDHCI_RESET_DATA BIT(2)
/*! SDMMC error interrupt status and control. */
#define SDHCI_ERR_INT_TIMEOUT 0x1
#define SDHCI_ERR_INT_CRC 0x2
#define SDHCI_ERR_INT_END_BIT 0x4
#define SDHCI_ERR_INT_INDEX 0x8
#define SDHCI_ERR_INT_DATA_TIMEOUT 0x10
#define SDHCI_ERR_INT_DATA_CRC 0x20
#define SDHCI_ERR_INT_DATA_END_BIT 0x40
#define SDHCI_ERR_INT_BUS_POWER 0x80
#define SDHCI_ERR_INT_AUTO_CMD_ERR 0x100
#define SDHCI_ERR_INT_ADMA_ERROR 0x200
/*! SDMMC interrupt status and control. 0x30/0x34. */
#define SDHCI_INT_RESPONSE BIT(0)
#define SDHCI_INT_DATA_END BIT(1)
#define SDHCI_INT_BLK_GAP BIT(2)
#define SDHCI_INT_DMA_END BIT(3)
#define SDHCI_INT_SPACE_AVAIL BIT(4) // Write buffer empty.
#define SDHCI_INT_DATA_AVAIL BIT(5) // Read buffer has data.
#define SDHCI_INT_CARD_INSERT BIT(6)
#define SDHCI_INT_CARD_REMOVE BIT(7)
#define SDHCI_INT_CARD_INT BIT(8)
#define SDHCI_INT_RETUNE BIT(12)
#define SDHCI_INT_ERROR BIT(15)
/*! SDMMC error interrupt status and control. 0x32/0x36. */
#define SDHCI_ERR_INT_TIMEOUT BIT(0)
#define SDHCI_ERR_INT_CRC BIT(1)
#define SDHCI_ERR_INT_END_BIT BIT(2)
#define SDHCI_ERR_INT_INDEX BIT(3)
#define SDHCI_ERR_INT_DATA_TIMEOUT BIT(4)
#define SDHCI_ERR_INT_DATA_CRC BIT(5)
#define SDHCI_ERR_INT_DATA_END_BIT BIT(6)
#define SDHCI_ERR_INT_BUS_POWER BIT(7)
#define SDHCI_ERR_INT_AUTO_CMD12 BIT(8)
#define SDHCI_ERR_INT_ADMA BIT(9)
#define SDHCI_ERR_INT_TUNE BIT(10)
#define SDHCI_ERR_INT_RSP BIT(11)
#define SDHCI_ERR_INT_TARGET_RSP BIT(12)
#define SDHCI_ERR_INT_SPI BIT(13)
#define SDHCI_ERR_INT_VND_BOOT_TMO BIT(14)
#define SDHCI_ERR_INT_VND_BOOT_ACK BIT(15)
#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
(SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \
SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
(SDHCI_ERR_INT_AUTO_CMD12 | SDHCI_ERR_INT_DATA_END_BIT | \
SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
/*! Host Capability 1. 0x40. */
#define SDHCI_CAP_TM_CLK_FREQ_MASK 0x3F
#define SDHCI_CAP_TM_UNIT_MHZ BIT(7)
#define SDHCI_CAP_BASE_CLK_FREQ_MASK (0xFFU << 8)
#define SDHCI_CAP_MAX_BLK_LEN_MASK (3U << 16)
#define SDHCI_CAP_EMMC_8BIT BIT(18)
#define SDHCI_CAP_ADMA2 BIT(19)
#define SDHCI_CAP_HISPD BIT(21)
#define SDHCI_CAP_SDMA BIT(22)
#define SDHCI_CAP_SUSPEND_RESUME BIT(23)
#define SDHCI_CAP_3_3_V BIT(24)
#define SDHCI_CAP_3_0_V BIT(25)
#define SDHCI_CAP_1_8_V BIT(26)
#define SDHCI_CAP_64BIT BIT(28)
#define SDHCI_CAP_ASYNC_INT BIT(29)
#define SDHCI_CAP_SLOT_TYPE_MASK (3U << 30)
#define SDHCI_CAP_SLOT_TYPE_REMOVABLE (0U << 30)
#define SDHCI_CAP_SLOT_TYPE_EMBEDDED (1U << 30)
#define SDHCI_CAP_SLOT_TYPE_SHARED (2U << 30)
#define SDHCI_CAP_SLOT_TYPE_UHS2 (3U << 30)
/*! Host Capability 2. 0x44. */
#define SDHCI_CAP_SDR50 BIT(0)
#define SDHCI_CAP_SDR5104 BIT(1)
#define SDHCI_CAP_DDR50 BIT(2)
#define SDHCI_CAP_UHS2 BIT(3)
#define SDHCI_CAP_DRV_TYPE_A BIT(4)
#define SDHCI_CAP_DRV_TYPE_C BIT(5)
#define SDHCI_CAP_DRV_TYPE_D BIT(6)
#define SDHCI_CAP_RSP_TIMER_CNT_MASK (0xFU << 8)
#define SDHCI_CAP_SDR50_TUNING BIT(13)
#define SDHCI_CAP_RSP_MODES_MASK (3U << 14)
#define SDHCI_CAP_CLK_MULT (0xFFU << 16)
#define SDHCI_CAP_ADMA3 BIT(27)
#define SDHCI_CAP_VDD2_1_8V BIT(28)
/*! SDMMC max current. 0x48 */
#define SDHCI_MAX_CURRENT_3_3_V_MASK (0xFFU << 0)
#define SDHCI_MAX_CURRENT_3_0_V_MASK (0xFFU << 8)
#define SDHCI_MAX_CURRENT_1_8_V_MASK (0xFFU << 16)
#define SDHCI_MAX_CURRENT_MULTIPLIER 4
/*! SDMMC max current. 0x4C */
#define SDHCI_MAX_CURRENT_1_8_V_VDD2_MASK (0xFFU << 0)
/*! SD bus speeds. */
#define UHS_SDR12_BUS_SPEED 0
@@ -193,11 +260,11 @@
#define SDHCI_TIMING_UHS_SDR25 9
#define SDHCI_TIMING_UHS_SDR50 10
#define SDHCI_TIMING_UHS_SDR104 11
#define SDHCI_TIMING_UHS_SDR82 12 // SDR104 with a 163.2MHz -> 81.6MHz clock.
#define SDHCI_TIMING_UHS_DDR50 13
#define SDHCI_TIMING_MMC_HS102 14
#define SDHCI_CAN_64BIT 0x10000000
#define SDHCI_TIMING_UHS_DDR50 12
// SDR104 with a 163.2MHz -> 81.6MHz clock.
#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC.
#define SDHCI_TIMING_UHS_DDR200 15
/*! SDMMC Low power features. */
#define SDMMC_POWER_SAVE_DISABLE 0
@@ -206,12 +273,16 @@
/*! Helper for SWITCH command argument. */
#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
#define HW_TAP_TUNING 0x100
#define INVALID_TAP 0x100
#define SAMPLING_WINDOW_SIZE_MIN 8
/*! SDMMC controller context. */
typedef struct _sdmmc_t
{
t210_sdmmc_t *regs;
u32 id;
u32 divisor;
u32 card_clock;
u32 clock_stopped;
int powersave_enabled;
int manual_cal;
@@ -249,13 +320,14 @@ int sdmmc_get_io_power(sdmmc_t *sdmmc);
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
void sdmmc_save_tap_value(sdmmc_t *sdmmc);
void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type);
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable);
int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd);
int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
bool sdmmc_get_sd_inserted();
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable);
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type);
void sdmmc_end(sdmmc_t *sdmmc);
void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);

184
bdk/storage/sdmmc_t210.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2019 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,92 +18,112 @@
#ifndef _SDMMC_T210_H_
#define _SDMMC_T210_H_
#include <assert.h>
#include <utils/types.h>
#define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000
#define TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE 0x80000000
#define TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE 0x80000000
#define TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD 0x80000000
#define TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK 0xFFFFFFF0
#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE 0x20000000
#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START 0x80000000
#define TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE 0x80000000
#define SDHCI_TEGRA_TUNING_TAP_HW_UPDATED BIT(17)
#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
#define SDHCI_TEGRA_DLLCAL_ACTIVE BIT(31)
#define SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD BIT(31)
#define SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK 0xF
#define SDHCI_TEGRA_AUTOCAL_SLW_OVERRIDE BIT(28)
#define SDHCI_TEGRA_AUTOCAL_ENABLE BIT(29)
#define SDHCI_TEGRA_AUTOCAL_START BIT(31)
#define SDHCI_TEGRA_AUTOCAL_ACTIVE BIT(31)
typedef struct _t210_sdmmc_t
{
vu32 sysad;
vu16 blksize;
vu16 blkcnt;
vu32 argument;
vu16 trnmod;
vu16 cmdreg;
vu32 rspreg0;
vu32 rspreg1;
vu32 rspreg2;
vu32 rspreg3;
vu32 bdata;
vu32 prnsts;
vu8 hostctl;
vu8 pwrcon;
vu8 blkgap;
vu8 wakcon;
vu16 clkcon;
vu8 timeoutcon;
vu8 swrst;
vu16 norintsts;
vu16 errintsts;
vu16 norintstsen; // Enable irq status.
vu16 errintstsen; // Enable irq status.
vu16 norintsigen; // Enable irq signal to LIC/GIC.
vu16 errintsigen; // Enable irq signal to LIC/GIC.
vu16 acmd12errsts;
vu16 hostctl2;
vu32 capareg;
vu32 capareg_1;
vu32 maxcurr;
vu8 rsvd0[4]; // 4C-4F reserved for more max current.
vu16 setacmd12err;
vu16 setinterr;
vu8 admaerr;
vu8 rsvd1[3]; // 55-57 reserved.
vu32 admaaddr;
vu32 admaaddr_hi;
vu8 rsvd2[156]; // 60-FB reserved.
vu16 slotintsts;
vu16 hcver;
vu32 venclkctl;
vu32 vensysswctl;
vu32 venerrintsts;
vu32 vencapover;
vu32 venbootctl;
vu32 venbootacktout;
vu32 venbootdattout;
vu32 vendebouncecnt;
vu32 venmiscctl;
vu32 maxcurrover;
vu32 maxcurrover_hi;
vu32 unk0[32]; // 0x12C
vu32 veniotrimctl;
vu32 vendllcalcfg;
vu32 vendllctl0;
vu32 vendllctl1;
vu32 vendllcalcfgsts;
vu32 ventunctl0;
vu32 ventunctl1;
vu32 ventunsts0;
vu32 ventunsts1;
vu32 venclkgatehystcnt;
vu32 venpresetval0;
vu32 venpresetval1;
vu32 venpresetval2;
vu32 sdmemcmppadctl;
vu32 autocalcfg;
vu32 autocalintval;
vu32 autocalsts;
vu32 iospare;
vu32 mcciffifoctl;
vu32 timeoutwcoal;
vu32 unk1;
/* 0x00 */ vu32 sysad; // sdma system address.
/* 0x04 */ vu16 blksize;
/* 0x06 */ vu16 blkcnt;
/* 0x08 */ vu32 argument;
/* 0x0C */ vu16 trnmod;
/* 0x0E */ vu16 cmdreg;
/* 0x10 */ vu32 rspreg0;
/* 0x14 */ vu32 rspreg1;
/* 0x18 */ vu32 rspreg2;
/* 0x1C */ vu32 rspreg3;
/* 0x20 */ vu32 bdata; // Buffer data port.
/* 0x24 */ vu32 prnsts;
/* 0x28 */ vu8 hostctl;
/* 0x29 */ vu8 pwrcon;
/* 0x2A */ vu8 blkgap;
/* 0x2B */ vu8 wakcon;
/* 0x2C */ vu16 clkcon;
/* 0x2E */ vu8 timeoutcon;
/* 0x2F */ vu8 swrst;
/* 0x30 */ vu16 norintsts; // Normal interrupt status.
/* 0x32 */ vu16 errintsts; // Error interrupt status.
/* 0x34 */ vu16 norintstsen; // Enable irq status.
/* 0x36 */ vu16 errintstsen; // Enable irq status.
/* 0x38 */ vu16 norintsigen; // Enable irq signal to LIC/GIC.
/* 0x3A */ vu16 errintsigen; // Enable irq signal to LIC/GIC.
/* 0x3C */ vu16 acmd12errsts;
/* 0x3E */ vu16 hostctl2;
// CAP0: 0x376CD08C.
// 12 MHz timeout clock. 208 MHz max base clock. 512B max block length. 8-bit support.
// ADMA2 support. HS25 support. SDMA support. No suspend/resume support. 3.3/3.0/1.8V support.
// 64bit addressing for V3/V4 support. Async IRQ support. All report as removable.
/* 0x40 */ vu32 capareg;
// CAP1: 0x10002F73.
// SDR50/SDR104 support. No DDR50 support. Drive A/B/C/D support.
// Timer re-tuning info from other source. SDR50 requires re-tuning.
// Tuning uses timer and transfers should be 4MB limited.
// ADMA3 not supported. 1.8V VDD2 supported.
/* 0x44 */ vu32 capareg_hi;
/* 0x48 */ vu32 maxcurr; // Get information by another method. Can be overriden via maxcurrover and maxcurrover_hi.
/* 0x4C */ vu32 maxcurr_hi;
/* 0x50 */ vu16 setacmd12err; // Force error in acmd12errsts.
/* 0x52 */ vu16 setinterr;
/* 0x54 */ vu8 admaerr;
/* 0x55 */ vu8 rsvd1[3]; // 55-57 reserved.
/* 0x58 */ vu32 admaaddr;
/* 0x5C */ vu32 admaaddr_hi;
/* 0x60 */ vu16 presets[11];
/* 0x76 */ vu16 rsvd2;
/* 0x78 */ vu32 adma3addr;
/* 0x7C */ vu32 adma3addr_hi;
/* 0x80 */ vu8 uhs2[124]; // 80-FB UHS-II.
/* 0xFC */ vu16 slotintsts;
/* 0xFE */ vu16 hcver; // 0x303 (4.00).
/* UHS-II range. Used for Vendor registers here */
/* 0x100 */ vu32 venclkctl;
/* 0x104 */ vu32 vensysswctl;
/* 0x108 */ vu32 venerrintsts;
/* 0x10C */ vu32 vencapover;
/* 0x110 */ vu32 venbootctl;
/* 0x114 */ vu32 venbootacktout;
/* 0x118 */ vu32 venbootdattout;
/* 0x11C */ vu32 vendebouncecnt;
/* 0x120 */ vu32 venmiscctl;
/* 0x124 */ vu32 maxcurrover;
/* 0x128 */ vu32 maxcurrover_hi;
/* 0x12C */ vu32 unk0[32]; // 0x12C
/* 0x1AC */ vu32 veniotrimctl;
/* 0x1B0 */ vu32 vendllcalcfg;
/* 0x1B4 */ vu32 vendllctl0;
/* 0x1B8 */ vu32 vendllctl1;
/* 0x1BC */ vu32 vendllcalcfgsts;
/* 0x1C0 */ vu32 ventunctl0;
/* 0x1C4 */ vu32 ventunctl1;
/* 0x1C8 */ vu32 ventunsts0;
/* 0x1CC */ vu32 ventunsts1;
/* 0x1D0 */ vu32 venclkgatehystcnt;
/* 0x1D4 */ vu32 venpresetval0;
/* 0x1D8 */ vu32 venpresetval1;
/* 0x1DC */ vu32 venpresetval2;
/* 0x1E0 */ vu32 sdmemcmppadctl;
/* 0x1E4 */ vu32 autocalcfg;
/* 0x1E8 */ vu32 autocalintval;
/* 0x1EC */ vu32 autocalsts;
/* 0x1F0 */ vu32 iospare;
/* 0x1F4 */ vu32 mcciffifoctl;
/* 0x1F8 */ vu32 timeoutwcoal;
} t210_sdmmc_t;
static_assert(sizeof(t210_sdmmc_t) == 0x1FC, "T210 SDMMC REG size is wrong!");
#endif