niklascfw
1b4a81239b
Replaces the old vendored BDK with the one from hekate v6.5.5 (CTCaer's 2025/2026 refactors: sdmmc, SE, minerva v1.6, display, heap, return value homogenisation). OmniNX additions re-applied on top: bq24193_charger_connected() and jc_clear_input(); s_vprintf now ships with the BDK. Ported to the new API: - sd_mount(), sdmmc_storage_* and ini_parse() now return 0 on success. The installer checked ini_parse() != 1, which would have made it miss manifest.ini and run every install as a clean install. - SD helpers come from bdk/storage/sd.c (source/nx_sd.* removed), ffsystem.c from the BDK, diskio.c/ffconf.h from hekate (ffconf keeps the sd:/ volume prefix). - minerva_init() needs the minerva storage; the installer still drops to 800 MHz afterwards. - Payload launch follows hekate (sd_file_read, hw_deinit); coreboot path removed upstream. - Stack moved to 0x96000000: the old 0x83100000 is inside the new heap. - GUI/USB/compression parts of the BDK are not built.
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019-2025 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BPMP_H_
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#define _BPMP_H_
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#include <utils/types.h>
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typedef enum
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{
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BPMP_MMU_MAINT_NOP = 0,
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BPMP_MMU_MAINT_CLEAN_PHY = 1,
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BPMP_MMU_MAINT_INVALID_PHY = 2,
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BPMP_MMU_MAINT_CLEAN_INVALID_PHY = 3,
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BPMP_MMU_MAINT_CLEAN_LINE = 9,
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BPMP_MMU_MAINT_INVALID_LINE = 10,
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BPMP_MMU_MAINT_CLEAN_INVALID_LINE = 11,
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BPMP_MMU_MAINT_CLEAN_WAY = 17,
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BPMP_MMU_MAINT_INVALID_WAY = 18,
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BPMP_MMU_MAINT_CLN_INV_WAY = 19
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} bpmp_maintenance_t;
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typedef struct _bpmp_mmu_entry_t
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{
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u32 start_addr;
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u32 end_addr;
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u32 attr;
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u32 enable;
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} bpmp_mmu_entry_t;
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typedef enum
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{
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BPMP_CLK_NORMAL, // 408MHz 0% - 136MHz APB.
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BPMP_CLK_HIGH_BOOST, // 544MHz 33% - 136MHz APB.
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BPMP_CLK_HIGH2_BOOST, // 563MHz 38% - 141MHz APB.
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BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
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BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
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//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
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BPMP_CLK_NUM
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} bpmp_freq_t;
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typedef enum
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{
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BPMP_STATE_STANDBY = 0, // 32KHz.
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BPMP_STATE_IDLE = 1,
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BPMP_STATE_RUN = 2,
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BPMP_STATE_IRQ = BIT(2),
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BPMP_STATE_FIQ = BIT(3),
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} bpmp_state_t;
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#define BPMP_CLK_BIN0_BOOST BPMP_CLK_HYPER_BOOST
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#define BPMP_CLK_BIN1_BOOST BPMP_CLK_SUPER_BOOST
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#define BPMP_CLK_BIN2_BOOST BPMP_CLK_HIGH2_BOOST
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#define BPMP_CLK_BIN3_BOOST BPMP_CLK_HIGH_BOOST
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#define BPMP_CLK_LOWEST_BOOST BPMP_CLK_BIN3_BOOST
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#define BPMP_CLK_LOWER_BOOST BPMP_CLK_BIN1_BOOST
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#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_BIN0_BOOST
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void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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void bpmp_clk_rate_relaxed(bool enable);
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void bpmp_clk_rate_get();
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void bpmp_clk_rate_set(bpmp_freq_t fid);
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void bpmp_state_set(bpmp_state_t state);
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void bpmp_usleep(u32 us);
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void bpmp_msleep(u32 ms);
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void bpmp_halt();
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#endif
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