492 lines
17 KiB
C
492 lines
17 KiB
C
/*
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* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#define EMC_INTSTATUS_0 0x0
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#define EMC_INTMASK_0 0x4
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#define EMC_DBG_0 0x8
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#define EMC_CFG_0 0xC
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#define EMC_ADR_CFG_0 0x10
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#define EMC_REFCTRL_0 0x20
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#define EMC_PIN_0 0x24
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#define EMC_TIMING_CONTROL_0 0x28
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#define EMC_RC_0 0x2C
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#define EMC_RFC_0 0x30
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#define EMC_RAS_0 0x34
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#define EMC_RP_0 0x38
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#define EMC_R2W_0 0x3C
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#define EMC_W2R_0 0x40
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#define EMC_R2P_0 0x44
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#define EMC_W2P_0 0x48
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#define EMC_RD_RCD_0 0x4C
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#define EMC_WR_RCD_0 0x50
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#define EMC_RRD_0 0x54
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#define EMC_REXT_0 0x58
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#define EMC_WDV_0 0x5C
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#define EMC_QUSE_0 0x60
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#define EMC_QRST_0 0x64
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#define EMC_QSAFE_0 0x68
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#define EMC_RDV_0 0x6C
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#define EMC_REFRESH_0 0x70
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#define EMC_BURST_REFRESH_NUM_0 0x74
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#define EMC_PDEX2WR_0 0x78
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#define EMC_PDEX2RD_0 0x7C
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#define EMC_PCHG2PDEN_0 0x80
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#define EMC_ACT2PDEN_0 0x84
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#define EMC_AR2PDEN_0 0x88
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#define EMC_RW2PDEN_0 0x8C
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#define EMC_TXSR_0 0x90
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#define EMC_TCKE_0 0x94
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#define EMC_TFAW_0 0x98
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#define EMC_TRPAB_0 0x9C
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#define EMC_TCLKSTABLE_0 0xA0
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#define EMC_TCLKSTOP_0 0xA4
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#define EMC_TREFBW_0 0xA8
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#define EMC_TPPD_0 0xAC
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#define EMC_ODT_WRITE_0 0xB0
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#define EMC_PDEX2MRR_0 0xB4
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#define EMC_WEXT_0 0xB8
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#define EMC_RFC_SLR_0 0xC0
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#define EMC_MRS_WAIT_CNT2_0 0xC4
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#define EMC_MRS_WAIT_CNT_0 0xC8
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#define EMC_MRS_0 0xCC
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#define EMC_EMRS_0 0xD0
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#define EMC_REF_0 0xD4
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#define EMC_PRE_0 0xD8
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#define EMC_NOP_0 0xDC
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#define EMC_SELF_REF_0 0xE0
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#define EMC_DPD_0 0xE4
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#define EMC_MRW_0 0xE8
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#define EMC_MRR_0 0xEC
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#define EMC_CMDQ_0 0xF0
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#define EMC_MC2EMCQ_0 0xF4
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#define EMC_FBIO_SPARE_0 0x100
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#define EMC_FBIO_CFG5_0 0x104
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#define EMC_FBIO_CFG6_0 0x114
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#define EMC_PDEX2CKE_0 0x118
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#define EMC_CKE2PDEN_0 0x11C
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#define EMC_CFG_RSV_0 0x120
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#define EMC_ACPD_CONTROL_0 0x124
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#define EMC_MPC_0 0x128
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#define EMC_EMRS2_0 0x12C
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#define EMC_EMRS3_0 0x130
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#define EMC_MRW2_0 0x134
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#define EMC_MRW3_0 0x138
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#define EMC_MRW4_0 0x13C
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#define EMC_CLKEN_OVERRIDE_0 0x140
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#define EMC_R2R_0 0x144
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#define EMC_W2W_0 0x148
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#define EMC_EINPUT_0 0x14C
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#define EMC_EINPUT_DURATION_0 0x150
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#define EMC_PUTERM_EXTRA_0 0x154
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#define EMC_TCKESR_0 0x158
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#define EMC_TPD_0 0x15C
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#define EMC_AUTO_CAL_CONFIG_0 0x2A4
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#define EMC_AUTO_CAL_INTERVAL_0 0x2A8
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#define EMC_AUTO_CAL_STATUS_0 0x2AC
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#define EMC_REQ_CTRL_0 0x2B0
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#define EMC_EMC_STATUS_0 0x2B4
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#define EMC_CFG_2_0 0x2B8
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#define EMC_CFG_DIG_DLL_0 0x2BC
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#define EMC_CFG_DIG_DLL_PERIOD_0 0x2C0
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#define EMC_DIG_DLL_STATUS_0 0x2C4
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#define EMC_CFG_DIG_DLL_1_0 0x2C8
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#define EMC_RDV_MASK_0 0x2CC
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#define EMC_WDV_MASK_0 0x2D0
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#define EMC_RDV_EARLY_MASK_0 0x2D4
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#define EMC_RDV_EARLY_0 0x2D8
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#define EMC_AUTO_CAL_CONFIG8_0 0x2DC
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#define EMC_ZCAL_INTERVAL_0 0x2E0
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#define EMC_ZCAL_WAIT_CNT_0 0x2E4
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#define EMC_ZCAL_MRW_CMD_0 0x2E8
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#define EMC_ZQ_CAL_0 0x2EC
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#define EMC_XM2COMPPADCTRL3_0 0x2F4
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#define EMC_AUTO_CAL_VREF_SEL_0_0 0x2F8
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#define EMC_AUTO_CAL_VREF_SEL_1_0 0x300
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#define EMC_XM2COMPPADCTRL_0 0x30C
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#define EMC_FDPD_CTRL_DQ_0 0x310
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#define EMC_FDPD_CTRL_CMD_0 0x314
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#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 0x318
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#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 0x31C
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#define EMC_SCRATCH0_0 0x324
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#define EMC_PMACRO_BRICK_CTRL_RFU1_0 0x330
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#define EMC_PMACRO_BRICK_CTRL_RFU2_0 0x334
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#define EMC_CMD_MAPPING_CMD0_0_0 0x380
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#define EMC_CMD_MAPPING_CMD0_1_0 0x384
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#define EMC_CMD_MAPPING_CMD0_2_0 0x388
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#define EMC_CMD_MAPPING_CMD1_0_0 0x38C
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#define EMC_CMD_MAPPING_CMD1_1_0 0x390
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#define EMC_CMD_MAPPING_CMD1_2_0 0x394
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#define EMC_CMD_MAPPING_CMD2_0_0 0x398
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#define EMC_CMD_MAPPING_CMD2_1_0 0x39C
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#define EMC_CMD_MAPPING_CMD2_2_0 0x3A0
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#define EMC_CMD_MAPPING_CMD3_0_0 0x3A4
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#define EMC_CMD_MAPPING_CMD3_1_0 0x3A8
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#define EMC_CMD_MAPPING_CMD3_2_0 0x3AC
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#define EMC_CMD_MAPPING_BYTE_0 0x3B0
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#define EMC_TR_TIMING_0_0 0x3B4
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#define EMC_TR_CTRL_0_0 0x3B8
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#define EMC_TR_CTRL_1_0 0x3BC
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#define EMC_SWITCH_BACK_CTRL_0 0x3C0
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#define EMC_TR_RDV_0 0x3C4
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#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 0x3C8
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#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 0x3CC
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#define EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 0x3D0
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#define EMC_AUTO_CAL_ 0x3D4
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#define EMC_SEL_DPD_CTRL_0 0x3D8
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#define EMC_PRE_REFRESH_REQ_CNT_0 0x3DC
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#define EMC_DYN_SELF_REF_CONTROL_0 0x3E0
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#define EMC_TXSRDLL_0 0x3E4
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#define EMC_CCFIFO_ADDR_0 0x3E8
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#define EMC_CCFIFO_DATA_0 0x3EC
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#define EMC_CCFIFO_STATUS_0 0x3F0
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#define EMC_TR_QPOP_0 0x3F4
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#define EMC_TR_RDV_MASK_0 0x3F8
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#define EMC_TR_QSAFE_0 0x3FC
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#define EMC_TR_QRST_0 0x400
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#define EMC_SWIZZLE_RANK0_BYTE0_0 0x404
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#define EMC_SWIZZLE_RANK0_BYTE1_0 0x408
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#define EMC_SWIZZLE_RANK0_BYTE2_0 0x40C
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#define EMC_SWIZZLE_RANK0_BYTE3_0 0x410
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#define EMC_SWIZZLE_RANK1_BYTE0_0 0x418
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#define EMC_SWIZZLE_RANK1_BYTE1_0 0x41C
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#define EMC_SWIZZLE_RANK1_BYTE2_0 0x420
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#define EMC_SWIZZLE_RANK1_BYTE3_0 0x424
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#define EMC_ISSUE_QRST_0 0x428
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#define EMC_PMC_SCRATCH1_0 0x440
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#define EMC_PMC_SCRATCH2_0 0x444
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#define EMC_PMC_SCRATCH3_0 0x448
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#define EMC_AUTO_CAL_CONFIG2_0 0x458
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#define EMC_AUTO_CAL_CONFIG3_0 0x45C
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#define EMC_TR_DVFS_0 0x460
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#define EMC_AUTO_CAL_CHANNEL_0 0x464
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#define EMC_IBDLY_0 0x468
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#define EMC_OBDLY_0 0x46C
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#define EMC_TXDSRVTTGEN_0 0x480
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#define EMC_WE_DURATION_0 0x48C
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#define EMC_WS_DURATION_0 0x490
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#define EMC_WEV_0 0x494
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#define EMC_WSV_0 0x498
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#define EMC_CFG_3_0 0x49C
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#define EMC_MRW5_0 0x4A0
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#define EMC_MRW6_0 0x4A4
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#define EMC_MRW7_0 0x4A8
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#define EMC_MRW8_0 0x4AC
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#define EMC_MRW9_0 0x4B0
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#define EMC_MRW10_0 0x4B4
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#define EMC_MRW11_0 0x4B8
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#define EMC_MRW12_0 0x4BC
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#define EMC_MRW13_0 0x4C0
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#define EMC_MRW14_0 0x4C4
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#define EMC_MRW15_0 0x4D0
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#define EMC_CFG_SYNC_0 0x4D4
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#define EMC_FDPD_CTRL_CMD_NO_RAMP_0 0x4D8
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#define EMC_WDV_CHK_0 0x4E0
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#define EMC_CFG_PIPE_2_0 0x554
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#define EMC_CFG_PIPE_CLK_0 0x558
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#define EMC_CFG_PIPE_1_0 0x55C
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#define EMC_CFG_PIPE_0 0x560
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#define EMC_QPOP_0 0x564
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#define EMC_QUSE_WIDTH_0 0x568
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#define EMC_PUTERM_WIDTH_0 0x56C
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#define EMC_BGBIAS_CTL0_0 0x570
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#define EMC_AUTO_CAL_CONFIG7_0 0x574
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#define EMC_XM2COMPPADCTRL2_0 0x578
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#define EMC_COMP_PAD_SW_CTRL_0 0x57C
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#define EMC_REFCTRL2_0 0x580
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#define EMC_FBIO_CFG7_0 0x584
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#define EMC_DATA_BRLSHFT_0_0 0x588
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#define EMC_DATA_BRLSHFT_1_0 0x58C
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#define EMC_RFCPB_0 0x590
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#define EMC_DQS_BRLSHFT_0_0 0x594
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#define EMC_DQS_BRLSHFT_1_0 0x598
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#define EMC_CMD_BRLSHFT_0_0 0x59C
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#define EMC_CMD_BRLSHFT_1_0 0x5A0
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#define EMC_CMD_BRLSHFT_2_0 0x5A4
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#define EMC_CMD_BRLSHFT_3_0 0x5A8
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#define EMC_QUSE_BRLSHFT_0_0 0x5AC
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#define EMC_AUTO_CAL_CONFIG4_0 0x5B0
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#define EMC_AUTO_CAL_CONFIG5_0 0x5B4
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#define EMC_QUSE_BRLSHFT_1_0 0x5B8
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#define EMC_QUSE_BRLSHFT_2_0 0x5BC
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#define EMC_CCDMW_0 0x5C0
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#define EMC_QUSE_BRLSHFT_3_0 0x5C4
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#define EMC_FBIO_CFG8_0 0x5C8
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#define EMC_AUTO_CAL_CONFIG6_0 0x5CC
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#define EMC_PROTOBIST_CONFIG_ADR_1_0 0x5D0
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#define EMC_PROTOBIST_CONFIG_ADR_2_0 0x5D4
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#define EMC_PROTOBIST_MISC_0 0x5D8
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#define EMC_PROTOBIST_WDATA_LOWER_0 0x5DC
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#define EMC_PROTOBIST_WDATA_UPPER_0 0x5E0
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#define EMC_PROTOBIST_RDATA_0 0x5EC
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#define EMC_DLL_CFG_0_0 0x5E4
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#define EMC_DLL_CFG_1_0 0x5E8
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#define EMC_CONFIG_SAMPLE_DELAY_0 0x5F0
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#define EMC_CFG_UPDATE_0 0x5F4
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#define EMC_PMACRO_QUSE_DDLL_RANK0_0_0 0x600
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#define EMC_PMACRO_QUSE_DDLL_RANK0_1_0 0x604
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#define EMC_PMACRO_QUSE_DDLL_RANK0_2_0 0x608
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#define EMC_PMACRO_QUSE_DDLL_RANK0_3_0 0x60C
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#define EMC_PMACRO_QUSE_DDLL_RANK0_4_0 0x610
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#define EMC_PMACRO_QUSE_DDLL_RANK0_5_0 0x614
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#define EMC_PMACRO_QUSE_DDLL_RANK1_0_0 0x620
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#define EMC_PMACRO_QUSE_DDLL_RANK1_1_0 0x624
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#define EMC_PMACRO_QUSE_DDLL_RANK1_2_0 0x628
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#define EMC_PMACRO_QUSE_DDLL_RANK1_3_0 0x62C
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#define EMC_PMACRO_QUSE_DDLL_RANK1_4_0 0x630
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#define EMC_PMACRO_QUSE_DDLL_RANK1_5_0 0x634
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 0x640
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 0x644
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 0x648
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 0x64C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 0x650
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 0x654
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 0x660
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 0x664
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 0x668
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 0x66C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 0x670
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 0x674
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 0x680
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 0x684
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 0x688
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 0x68C
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 0x690
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 0x694
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 0x6A0
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 0x6A4
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 0x6A8
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 0x6AC
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 0x6B0
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 0x6B4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 0x6C0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 0x6C4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 0x6C8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 0x6CC
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 0x6D0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 0x6D4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 0x6E0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 0x6E4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 0x6E8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 0x6EC
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 0x6F0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 0x6F4
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#define EMC_PMACRO_AUTOCAL_CFG_0_0 0x700
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#define EMC_PMACRO_AUTOCAL_CFG_1_0 0x704
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#define EMC_PMACRO_AUTOCAL_CFG_2_0 0x708
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#define EMC_PMACRO_TX_PWRD_0_0 0x720
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#define EMC_PMACRO_TX_PWRD_1_0 0x724
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#define EMC_PMACRO_TX_PWRD_2_0 0x728
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#define EMC_PMACRO_TX_PWRD_3_0 0x72C
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#define EMC_PMACRO_TX_PWRD_4_0 0x730
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#define EMC_PMACRO_TX_PWRD_5_0 0x734
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#define EMC_PMACRO_TX_SEL_CLK_SRC_0_0 0x740
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#define EMC_PMACRO_TX_SEL_CLK_SRC_1_0 0x744
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#define EMC_PMACRO_TX_SEL_CLK_SRC_2_0 0x748
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#define EMC_PMACRO_TX_SEL_CLK_SRC_3_0 0x74C
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#define EMC_PMACRO_TX_SEL_CLK_SRC_4_0 0x750
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#define EMC_PMACRO_TX_SEL_CLK_SRC_5_0 0x754
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#define EMC_PMACRO_DDLL_BYPASS_0 0x760
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#define EMC_PMACRO_DDLL_PWRD_0_0 0x770
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#define EMC_PMACRO_DDLL_PWRD_1_0 0x774
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#define EMC_PMACRO_DDLL_PWRD_2_0 0x778
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#define EMC_PMACRO_CMD_CTRL_0_0 0x780
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#define EMC_PMACRO_CMD_CTRL_1_0 0x784
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#define EMC_PMACRO_CMD_CTRL_2_0 0x788
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#define MC_INTSTATUS_0 0x000
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#define MC_INTMASK_0 0x004
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#define MC_ERR_STATUS_0 0x008
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#define MC_ERR_ADR_0 0x00C
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#define MC_SMMU_CONFIG_0 0x010
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#define MC_SMMU_PTB_ASID_0 0x01C
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#define MC_SMMU_PTB_DATA_0 0x020
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#define MC_SMMU_TLB_FLUSH_0 0x030
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#define MC_SMMU_PTC_FLUSH_0_0 0x034
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#define MC_EMEM_CFG_0 0x050
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#define MC_EMEM_ADR_CFG_0 0x054
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#define MC_EMEM_ARB_CFG_0 0x090
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#define MC_EMEM_ARB_OUTSTANDING_REQ_0 0x094
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#define MC_EMEM_ARB_TIMING_RCD_0 0x098
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#define MC_EMEM_ARB_TIMING_RP_0 0x09C
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#define MC_EMEM_ARB_TIMING_RC_0 0x0A0
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#define MC_EMEM_ARB_TIMING_RAS_0 0x0A4
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#define MC_EMEM_ARB_TIMING_FAW_0 0x0A8
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#define MC_EMEM_ARB_TIMING_RRD_0 0x0AC
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#define MC_EMEM_ARB_TIMING_RAP2PRE_0 0x0B0
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#define MC_EMEM_ARB_TIMING_WAP2PRE_0 0x0B4
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#define MC_EMEM_ARB_TIMING_R2R_0 0x0B8
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#define MC_EMEM_ARB_TIMING_W2W_0 0x0BC
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#define MC_EMEM_ARB_TIMING_R2W_0 0x0C0
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#define MC_EMEM_ARB_TIMING_W2R_0 0x0C4
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#define MC_EMEM_ARB_MISC2_0 0x0C8
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#define MC_EMEM_ARB_DA_TURNS_0 0x0D0
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#define MC_EMEM_ARB_DA_COVERS_0 0x0D4
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#define MC_EMEM_ARB_MISC0_0 0x0D8
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#define MC_EMEM_ARB_MISC1_0 0x0DC
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#define MC_TIMING_CONTROL_0 0xFC
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#define MC_EMEM_ARB_RING1_THROTTLE_0 0x0E0
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#define MC_CLIENT_HOTRESET_CTRL_0 0x200
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#define MC_CLIENT_HOTRESET_STATUS_0 0x204
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#define MC_SMMU_AFI_ASID_0 0x238
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#define MC_SMMU_DC_ASID_0 0x240
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#define MC_SMMU_DCB_ASID_0 0x244
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#define MC_SMMU_HC_ASID_0 0x250
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#define MC_SMMU_HDA_ASID_0 0x254
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#define MC_SMMU_ISP2_ASID_0 0x258
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#define MC_SMMU_MSENC_NVENC_ASID_0 0x264
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#define MC_SMMU_NV_ASID_0 0x268
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#define MC_SMMU_NV2_ASID_0 0x26C
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#define MC_SMMU_PPCS_ASID_0 0x270
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#define MC_SMMU_SATA_ASID_0 0x274
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#define MC_SMMU_VI_ASID_0 0x280
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#define MC_SMMU_VIC_ASID_0 0x284
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#define MC_SMMU_XUSB_HOST_ASID_0 0x288
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#define MC_SMMU_XUSB_DEV_ASID_0 0x28C
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#define MC_SMMU_TSEC_ASID_0 0x294
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#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
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#define MC_LATENCY_ALLOWANCE_DC_0 0x2E8
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#define MC_LATENCY_ALLOWANCE_DC_1 0x2EC
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#define MC_LATENCY_ALLOWANCE_DCB_0 0x2F4
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#define MC_LATENCY_ALLOWANCE_DCB_1 0x2F8
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#define MC_LATENCY_ALLOWANCE_HC_0 0x310
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#define MC_LATENCY_ALLOWANCE_HC_1 0x314
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#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
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#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
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#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
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#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
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#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
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#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
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#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
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#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
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#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
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#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
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#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
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#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
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#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
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#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
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#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
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#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
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#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
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#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
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#define MC_DIS_PTSA_RATE_0 0x41C
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#define MC_DIS_PTSA_MIN_0 0x420
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#define MC_DIS_PTSA_MAX_0 0x424
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#define MC_DISB_PTSA_RATE_0 0x428
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#define MC_DISB_PTSA_MIN_0 0x42C
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#define MC_DISB_PTSA_MAX_0 0x430
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#define MC_VE_PTSA_RATE_0 0x434
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#define MC_VE_PTSA_MIN_0 0x438
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#define MC_VE_PTSA_MAX_0 0x43C
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#define MC_MLL_MPCORER_PTSA_RATE_0 0x44C
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#define MC_RING1_PTSA_RATE_0 0x47C
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#define MC_RING1_PTSA_MIN_0 0x480
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#define MC_RING1_PTSA_MAX_0 0x484
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#define MC_PCX_PTSA_RATE_0 0x4AC
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#define MC_PCX_PTSA_MIN_0 0x4B0
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#define MC_PCX_PTSA_MAX_0 0x4B4
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#define MC_MSE_PTSA_RATE_0 0x4C4
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#define MC_MSE_PTSA_MIN_0 0x4C8
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#define MC_MSE_PTSA_MAX_0 0x4CC
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#define MC_AHB_PTSA_RATE_0 0x4DC
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#define MC_AHB_PTSA_MIN_0 0x4E0
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#define MC_AHB_PTSA_MAX_0 0x4E4
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#define MC_APB_PTSA_RATE_0 0x4E8
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#define MC_APB_PTSA_MIN_0 0x4EC
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#define MC_APB_PTSA_MAX_0 0x4F0
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#define MC_FTOP_PTSA_RATE_0 0x50C
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#define MC_HOST_PTSA_RATE_0 0x518
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#define MC_HOST_PTSA_MIN_0 0x51C
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#define MC_HOST_PTSA_MAX_0 0x520
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#define MC_USBX_PTSA_RATE_0 0x524
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#define MC_USBX_PTSA_MIN_0 0x528
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#define MC_USBX_PTSA_MAX_0 0x52C
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#define MC_USBD_PTSA_RATE_0 0x530
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#define MC_USBD_PTSA_MIN_0 0x534
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#define MC_USBD_PTSA_MAX_0 0x538
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#define MC_GK_PTSA_RATE_0 0x53C
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#define MC_GK_PTSA_MIN_0 0x540
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#define MC_GK_PTSA_MAX_0 0x544
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#define MC_AUD_PTSA_RATE_0 0x548
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#define MC_AUD_PTSA_MIN_0 0x54C
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#define MC_AUD_PTSA_MAX_0 0x550
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#define MC_VICPC_PTSA_RATE_0 0x554
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#define MC_VICPC_PTSA_MIN_0 0x558
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#define MC_VICPC_PTSA_MAX_0 0x55C
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#define MC_JPG_PTSA_RATE_0 0x584
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#define MC_JPG_PTSA_MIN_0 0x588
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#define MC_JPG_PTSA_MAX_0 0x58C
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#define MC_GK2_PTSA_RATE_0 0x610
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#define MC_GK2_PTSA_MIN_0 0x614
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#define MC_GK2_PTSA_MAX_0 0x618
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#define MC_SDM_PTSA_RATE_0 0x61C
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#define MC_SDM_PTSA_MIN_0 0x620
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#define MC_SDM_PTSA_MAX_0 0x624
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#define MC_HDAPC_PTSA_RATE_0 0x628
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#define MC_HDAPC_PTSA_MIN_0 0x62C
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#define MC_HDAPC_PTSA_MAX_0 0x630
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#define MC_SEC_CARVEOUT_BOM_0 0x670
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#define MC_SEC_CARVEOUT_SIZE_MB_0 0x674
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 0x690
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 0x694
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 0x698
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 0x69C
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 0x6A0
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#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 0x6A4
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#define MC_EMEM_ARB_TIMING_RFCPB_0 0x6C0
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#define MC_EMEM_ARB_TIMING_CCDMW_0 0x6C4
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#define MC_EMEM_ARB_REFPB_HP_CTRL_0 0x6F0
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#define MC_EMEM_ARB_REFPB_BANK_CTRL_0 0x6F4
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#define MC_PTSA_GRANT_DECREMENT_0 0x960
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#define MC_CLIENT_HOTRESET_CTRL_1 0x970
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#define MC_CLIENT_HOTRESET_STATUS_1 0x974
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#define MC_SMMU_PTC_FLUSH_1 0x9B8
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#define MC_SMMU_DC1_ASID_0 0xA88
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#define MC_SMMU_SDMMC1A_ASID_0 0xA94
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#define MC_SMMU_SDMMC2A_ASID_0 0xA98
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#define MC_SMMU_SDMMC3A_ASID_0 0xA9C
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#define MC_SMMU_SDMMC4A_ASID_0 0xAA0
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#define MC_SMMU_ISP2B_ASID_0 0xAA4
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#define MC_SMMU_GPU_ASID_0 0xAA8
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#define MC_SMMU_GPUB_ASID_0 0xAAC
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#define MC_SMMU_PPCS2_ASID_0 0xAB0
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#define MC_SMMU_NVDEC_ASID_0 0xAB4
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#define MC_SMMU_APE_ASID_0 0xAB8
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#define MC_SMMU_SE_ASID_0 0xABC
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#define MC_SMMU_NVJPG_ASID_0 0xAC0
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#define MC_SMMU_HC1_ASID_0 0xAC4
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#define MC_SMMU_SE1_ASID_0 0xAC8
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#define MC_SMMU_AXIAP_ASID_0 0xACC
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#define MC_SMMU_ETR_ASID_0 0xAD0
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#define MC_SMMU_TSECB_ASID_0 0xAD4
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#define MC_SMMU_TSEC1_ASID_0 0xAD8
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#define MC_SMMU_TSECB1_ASID_0 0xADC
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#define MC_SMMU_NVDEC1_ASID_0 0xAE0
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#define MC_EMEM_ARB_DHYST_CTRL_0 0xBCC
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
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#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_0 0xC00
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#define MC_SECURITY_CARVEOUT2_BOM_0 0xC5C
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#define MC_SECURITY_CARVEOUT3_BOM_0 0xCAC |