127 lines
3.1 KiB
C++
127 lines
3.1 KiB
C++
/*
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* Copyright (c) 2014 - 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Mikko Perttunen <mperttunen@nvidia.com>
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*
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* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#include <switch.h>
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#include <hocclk.h>
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namespace soctherm {
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#define R_UNLESS(rc) \
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do { \
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if (R_FAILED(rc)) { \
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return; \
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} \
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} while (0)
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struct TSensorConfig {
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u32 tall;
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u32 tiddq_en;
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u32 ten_count;
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u32 pdiv;
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u32 pdiv_ate;
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u32 tsample;
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u32 tsample_ate;
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};
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struct FuseCorrCoeff {
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s32 alpha;
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s32 beta;
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};
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struct TSensorGroup {
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const char *name;
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u8 id;
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u16 sensor_temp_offset;
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u32 sensor_temp_mask;
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u32 pdiv_mask;
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u32 pllx_hotspot_diff;
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u32 pllx_hotspot_mask;
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u32 hw_pllx_offset_mask;
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u32 hw_pllx_offset_en_mask;
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u32 thermtrip_enable_mask;
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u32 thermtrip_any_en_mask;
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u32 thermtrip_threshold_mask;
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u16 thermctl_lvl0_offset;
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u32 thermctl_isr_mask;
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u32 thermctl_lvl0_up_thresh_mask;
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u32 thermctl_lvl0_dn_thresh_mask;
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};
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struct TSensorGroupOffsets {
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u32 max;
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u32 min;
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u32 hw_offsetting_en;
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const TSensorGroup *ttg;
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};
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struct TSensor {
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const char *name;
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const u32 base;
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const TSensorConfig *config;
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const u32 calib_fuse_offset;
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const FuseCorrCoeff fuse_corr;
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const TSensorGroup *group;
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};
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struct TSensorFuse {
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u32 fuse_base_cp_mask;
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u32 fuse_base_cp_shift;
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u32 fuse_base_ft_mask;
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u32 fuse_base_ft_shift;
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u32 fuse_shift_ft_mask;
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u32 fuse_shift_ft_shift;
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u32 fuse_spare_realignment;
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};
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struct TSensorSharedCalib {
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u32 base_cp;
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u32 base_ft;
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u32 actual_temp_cp;
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u32 actual_temp_ft;
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};
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enum SocthermTSensor : u32 {
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SocthermTSensor_CPU0 = 0,
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SocthermTSensor_CPU1 = 1,
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SocthermTSensor_CPU2 = 2,
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SocthermTSensor_CPU3 = 3,
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SocthermTSensor_GPU = 4,
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SocthermTSensor_PLLX = 5,
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SocthermTSensor_MEM0 = 6,
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SocthermTSensor_MEM1 = 7,
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SocthermTSensor_EnumMax = 8,
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};
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struct TSensorTemps {
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s32 cpu;
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s32 gpu;
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s32 mem;
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s32 pllx;
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};
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void Initialize();
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void ReadSensors(TSensorTemps &temps);
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}
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