54 lines
2.5 KiB
Diff
54 lines
2.5 KiB
Diff
diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c
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index 00ec355..da4b149 100644
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--- a/bdk/mem/sdram.c
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+++ b/bdk/mem/sdram.c
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@@ -34,6 +34,8 @@
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#include <soc/t210.h>
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#include <utils/util.h>
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+#define DRAM_OVERVOLT 600000 // default: 600mV
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+
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#define CONFIG_SDRAM_KEEP_ALIVE
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typedef struct _sdram_vendor_patch_t
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@@ -1481,6 +1483,11 @@ static void _sdram_init_t210b01()
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{
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const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01();
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+#ifdef DRAM_OVERVOLT
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+ // Set DRAM voltage.
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+ max7762x_regulator_set_voltage(REGULATOR_77812_DRAM, DRAM_OVERVOLT);
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+#endif
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+
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// VDDP Select.
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PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
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usleep(params->pmc_vddp_sel_wait);
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diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c
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index a7d30ce..376c87e 100644
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--- a/bdk/power/max7762x.c
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+++ b/bdk/power/max7762x.c
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@@ -92,7 +92,7 @@ static const max77620_regulator_t _pmic_regulators[] = {
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{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
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//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
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- //{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
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+ { "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
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};
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static u8 _max77812_get_address()
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diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h
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index 3478530..d01f787 100644
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--- a/bdk/power/max7762x.h
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+++ b/bdk/power/max7762x.h
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@@ -62,8 +62,8 @@
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#define REGULATOR_GPU0 14
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#define REGULATOR_CPU1 15
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//#define REGULATOR_GPU1 16
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-//#define REGULATOR_GPU1 17
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-#define REGULATOR_MAX 15
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+#define REGULATOR_77812_DRAM 16
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+#define REGULATOR_MAX 16
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_GPU_I2C_ADDR 0x1C
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