950 lines
52 KiB
C++
950 lines
52 KiB
C++
/*
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* Copyright (C) Switch-OC-Suite
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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//#define EXPERIMENTAL
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#pragma once
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#include <stratosphere.hpp>
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namespace ams::ldr {
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// RAM(Emc) clockrates:
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// 1862400, 1894400, 1932800, 1996800, 2064000, 2099200, 2131200
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// Other values might work as well
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// RAM overclock could be UNSTABLE and generate graphical glitches / instabilities / NAND corruption
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// 1862400/1996800 has been tested stable for all DRAM chips
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constexpr u32 EmcClock = 1996800;
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// CPU max clockrate:
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// >= 2193000 will enable overvolting
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constexpr u32 CpuMaxClock = 2397000;
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// CPU max voltage
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constexpr u32 CpuVoltageLimit = 1220; // default max 1120mV
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static_assert(CpuVoltageLimit <= 1250);
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namespace pcv {
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typedef struct {
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s32 c0 = 0;
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s32 c1 = 0;
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s32 c2 = 0;
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s32 c3 = 0;
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s32 c4 = 0;
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s32 c5 = 0;
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} cvb_coefficients;
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typedef struct {
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u64 freq;
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cvb_coefficients cvb_dfll_param;
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cvb_coefficients cvb_pll_param; // only c0 is reserved
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} cpu_freq_cvb_table_t;
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typedef struct {
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u64 freq;
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cvb_coefficients cvb_dfll_param; // empty, dfll clock source not selected
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cvb_coefficients cvb_pll_param;
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} gpu_cvb_pll_table_t;
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typedef struct {
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u64 freq;
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s32 volt[4] = {0};
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} emc_dvb_dvfs_table_t;
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/* CPU */
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constexpr u32 NewCpuVoltageScaled = CpuVoltageLimit * 1000;
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// TODO: correctly derive c0-c1 dfll coefficients
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constexpr cpu_freq_cvb_table_t NewCpuTables[] = {
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// OldCpuTables
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// { 204000, { 721589, -12695, 27 }, { 1120000 } },
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// { 306000, { 747134, -14195, 27 }, { 1120000 } },
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// { 408000, { 776324, -15705, 27 }, { 1120000 } },
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// { 510000, { 809160, -17205, 27 }, { 1120000 } },
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// { 612000, { 845641, -18715, 27 }, { 1120000 } },
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// { 714000, { 885768, -20215, 27 }, { 1120000 } },
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// { 816000, { 929540, -21725, 27 }, { 1120000 } },
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// { 918000, { 976958, -23225, 27 }, { 1120000 } },
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// { 1020000, { 1028021, -24725, 27 }, { 1120000 } },
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// { 1122000, { 1082730, -26235, 27 }, { 1120000 } },
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// { 1224000, { 1141084, -27735, 27 }, { 1120000 } },
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// { 1326000, { 1203084, -29245, 27 }, { 1120000 } },
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// { 1428000, { 1268729, -30745, 27 }, { 1120000 } },
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// { 1581000, { 1374032, -33005, 27 }, { 1120000 } },
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// { 1683000, { 1448791, -34505, 27 }, { 1120000 } },
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// { 1785000, { 1527196, -36015, 27 }, { 1120000 } },
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// { 1887000, { 1609246, -37515, 27 }, { 1120000 } },
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// { 1963500, { 1675751, -38635, 27 }, { 1120000 } },
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{ 2091000, { 1785520, -40523, 27 }, { NewCpuVoltageScaled } },
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{ 2193000, { 1878755, -42027, 27 }, { NewCpuVoltageScaled } },
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{ 2295000, { 1975655, -43531, 27 }, { NewCpuVoltageScaled } },
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{ 2397000, { 2076220, -45036, 27 }, { NewCpuVoltageScaled } },
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};
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static_assert(sizeof(NewCpuTables) <= sizeof(cpu_freq_cvb_table_t)*14);
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/* GPU */
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constexpr gpu_cvb_pll_table_t NewGpuTables[] = {
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// OldGpuTables
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// { 76800, {}, { 610000, } },
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// { 153600, {}, { 610000, } },
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// { 230400, {}, { 610000, } },
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// { 307200, {}, { 610000, } },
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// { 460800, {}, { 610000, } },
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// { 537600, {}, { 801688, -10900, -163, 298, -10599, 162 } },
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// { 614400, {}, { 824214, -5743, -452, 238, -6325, 81 } },
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// { 691200, {}, { 848830, -3903, -552, 119, -4030, -2 } },
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// { 768000, {}, { 891575, -4409, -584, 0, -2849, 39 } },
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// { 844800, {}, { 940071, -5367, -602, -60, -63, -93 } },
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// { 921600, {}, { 986765, -6637, -614, -179, 1905, -13 } },
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// { 998400, {}, { 1098475, -13529, -497, -179, 3626, 9 } },
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// { 1075200, {}, { 1163644, -12688, -648, 0, 1077, 40 } },
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// { 1152000, {}, { 1204812, -9908, -830, 0, 1469, 110 } },
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// { 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313 } },
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// { 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559 } },
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{ 1305600, {}, { 1374130, -13725, -859, 0, 4442, 576 } },
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};
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static_assert(sizeof(NewGpuTables) <= sizeof(gpu_cvb_pll_table_t)*15);
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/* EMC */
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// DvbTable is all about frequency scaling along with CPU core voltage, no need to care about this for now.
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// constexpr emc_dvb_dvfs_table_t EmcDvbTable[6] =
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// {
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// { 204000, { 637, 637, 637, } },
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// { 408000, { 637, 637, 637, } },
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// { 800000, { 637, 637, 637, } },
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// { 1065600, { 637, 637, 637, } },
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// { 1331200, { 650, 637, 637, } },
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// { 1600000, { 675, 650, 637, } },
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// };
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// Mariko have 3 mtc tables (204/1331/1600 MHz), only these 3 frequencies could be set.
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// Mariko mtc tables starting from rev, see mtc_timing_table.hpp for parameters.
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// All mariko mtc tables will be patched to simplify the procedure.
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#include "mtc_timing_table.hpp"
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void AdjustMtcTable(MarikoMtcTable* table, MarikoMtcTable* ref)
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{
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/* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
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* https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
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* Section 18.11: MC Registers
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*
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* Retail Mariko: 200FBGA 16Gb DDP LPDDR4X SDRAM x 2
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* x16/Ch, 1Ch/die, Double-die, 2Ch, 1CS(rank), 8Gb density per die
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* 64Mb x 16DQ x 8banks x 2channels = 2048MB (x32DQ) per package
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*
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* Devkit Mariko: 200FBGA 32Gb DDP LPDDR4X SDRAM x 2
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* x16/Ch, 1Ch/die, Quad-die, 2Ch, 2CS(rank), 8Gb density per die
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* X1+ EMC can R/W to both ranks at the same time, resulting in doubled DQ
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* 64Mb x 32DQ x 8banks x 2channels = 4096MB (x64DQ) per package
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*
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* If you have access to LPDDR4(X) specs or datasheets (from manufacturers or Google),
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* you'd better calculate timings yourself rather than relying on following algorithm.
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*/
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#define ADJUST_PARAM(TARGET, REF) TARGET = std::ceil(REF + ((EmcClock-1331200)*(TARGET-REF))/(1600000-1331200));
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#define ADJUST_PARAM_TABLE(TABLE, PARAM, REF) ADJUST_PARAM(TABLE->PARAM, REF->PARAM)
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#define ADJUST_PARAM_ALL_REG(TABLE, PARAM, REF) \
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ADJUST_PARAM_TABLE(TABLE, burst_regs.PARAM, REF) \
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ADJUST_PARAM_TABLE(TABLE, shadow_regs_ca_train.PARAM, REF) \
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ADJUST_PARAM_TABLE(TABLE, shadow_regs_rdwr_train.PARAM, REF)
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#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE)\
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TABLE->burst_regs.PARAM = VALUE; \
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TABLE->shadow_regs_ca_train.PARAM = VALUE; \
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TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
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/* Timings that are available in or can be derived from LPDDR4X datasheet or TRM */
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{
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// tCK_avg (average clock period) in ns
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const double tCK_avg = (EmcClock == 2131200) ? 0.468 : 1000'000. / EmcClock;
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// tRPpb (row precharge time per bank) in ns
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const u32 tRPpb = 18;
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// tRPab (row precharge time all banks) in ns
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const u32 tRPab = 21;
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// tRAS (row active time) in ns
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const u32 tRAS = 42;
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// tRC (ACTIVATE-ACTIVATE command period same bank) in ns
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const u32 tRC = tRPpb + tRAS;
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// tRFCab (refresh cycle time all banks) in ns for 8Gb density
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const u32 tRFCab = 280;
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// tRFCpb (refresh cycle time per bank) in ns for 8Gb density
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const u32 tRFCpb = 140;
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// tRCD (RAS-CAS delay) in ns
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const u32 tRCD = 18;
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// tRRD (Active bank-A to Active bank-B) in ns
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const double tRRD = (EmcClock == 2131200) ? 7.5 : 10.;
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// tREFpb (average refresh interval per bank) in ns for 8Gb density
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const u32 tREFpb = 488;
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// tREFab (average refresh interval all 8 banks) in ns for 8Gb density
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// const u32 tREFab = tREFpb * 8;
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// #_of_rows per die for 8Gb density
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const u32 numOfRows = 65536;
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// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
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// emc_clk_period = dram_clk / 2;
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// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
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const u32 REFRESH = std::ceil((double(tREFpb) * EmcClock / numOfRows * (1.048) / 2 - 64)) / 4 * 4;
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// tPDEX2WR, tPDEX2RD (timing delay from exiting powerdown mode to a write/read command) in ns
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const u32 tPDEX2 = 10;
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// [Guessed] tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
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const u32 tACT2PDEN = 14;
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// [Guessed] tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
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const double tPDEX2MRR = 28.75;
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// [Guessed] tCKE2PDEN (timing delay from turning off CKE to power-down entry) in ns
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const double tCKE2PDEN = 8.5;
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// tXSR (SELF REFRESH exit to next valid command delay) in ns
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const double tXSR = tRFCab + 7.5;
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// tCKE (minimum CKE high pulse width) in ns
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const u32 tCKE = 8;
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// tCKELPD (minimum CKE low pulse width in SELF REFRESH) in ns
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const u32 tCKELPD = 15;
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// [Guessed] tPD (minimum CKE low pulse width in power-down mode) in ns
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const double tPD = 7.5;
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// tFAW (Four-bank Activate Window) in ns
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const u32 tFAW = (EmcClock == 2131200) ? 30 : 40;
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#define GET_CYCLE_CEIL(PARAM) std::ceil(double(PARAM) / tCK_avg)
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WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
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WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
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WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
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WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
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WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
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WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
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WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
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WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
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WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
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WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
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WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tPDEX2));
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WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tPDEX2));
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WRITE_PARAM_ALL_REG(table, emc_act2pden,GET_CYCLE_CEIL(tACT2PDEN));
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WRITE_PARAM_ALL_REG(table, emc_cke2pden,GET_CYCLE_CEIL(tCKE2PDEN));
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WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
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WRITE_PARAM_ALL_REG(table, emc_txsr, GET_CYCLE_CEIL(tXSR));
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WRITE_PARAM_ALL_REG(table, emc_txsrdll, GET_CYCLE_CEIL(tXSR));
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WRITE_PARAM_ALL_REG(table, emc_tcke, GET_CYCLE_CEIL(tCKE));
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WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tCKELPD));
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WRITE_PARAM_ALL_REG(table, emc_tpd, GET_CYCLE_CEIL(tPD));
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WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
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WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
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WRITE_PARAM_ALL_REG(table, emc_trefbw, REFRESH + 64);
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constexpr u32 MC_ARB_DIV = 4; // ?
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table->burst_mc_regs.mc_emem_arb_timing_rcd = std::ceil(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2);
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table->burst_mc_regs.mc_emem_arb_timing_rp = std::ceil(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1);
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table->burst_mc_regs.mc_emem_arb_timing_rc = std::ceil(std::max(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb))/ MC_ARB_DIV);
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table->burst_mc_regs.mc_emem_arb_timing_ras = std::ceil(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2);
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table->burst_mc_regs.mc_emem_arb_timing_faw = std::ceil(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV - 1);
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table->burst_mc_regs.mc_emem_arb_timing_rrd = std::ceil(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV - 1);
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table->burst_mc_regs.mc_emem_arb_timing_rap2pre = std::ceil(table->burst_regs.emc_r2p / MC_ARB_DIV);
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table->burst_mc_regs.mc_emem_arb_timing_wap2pre = std::ceil(table->burst_regs.emc_w2p / MC_ARB_DIV);
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table->burst_mc_regs.mc_emem_arb_timing_r2w = std::ceil(table->burst_regs.emc_r2w / MC_ARB_DIV + 1);
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table->burst_mc_regs.mc_emem_arb_timing_w2r = std::ceil(table->burst_regs.emc_w2r / MC_ARB_DIV + 1);
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table->burst_mc_regs.mc_emem_arb_timing_rfcpb = std::ceil(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV + 1); // ?
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}
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ADJUST_PARAM_ALL_REG(table, emc_r2w, ref);
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ADJUST_PARAM_ALL_REG(table, emc_w2r, ref);
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ADJUST_PARAM_ALL_REG(table, emc_r2p, ref);
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ADJUST_PARAM_ALL_REG(table, emc_w2p, ref);
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ADJUST_PARAM_ALL_REG(table, emc_trtm, ref);
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ADJUST_PARAM_ALL_REG(table, emc_twtm, ref);
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ADJUST_PARAM_ALL_REG(table, emc_tratm, ref);
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ADJUST_PARAM_ALL_REG(table, emc_twatm, ref);
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ADJUST_PARAM_ALL_REG(table, emc_rw2pden, ref);
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ADJUST_PARAM_ALL_REG(table, emc_tclkstop, ref);
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ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2, ref); // EMC_DLL_CFG_2_0: level select for VDDA?
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// ADJUST_PARAM_TABLE(table, dram_timings.rl); // not used on Mariko
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ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref);
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ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref);
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// ADJUST_PARAM_TABLE(table, min_mrs_wait); // not used on LPDDR4X
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// ADJUST_PARAM_TABLE(table, latency); // not used
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/* Patch PLLMB divisors */
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{
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// Calculate DIVM and DIVN (clock divisors)
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// Common PLL oscillator is 38.4 MHz
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// PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
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u32 divm = 1;
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u32 divn = EmcClock / 38400;
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u32 remainder = EmcClock % 38400;
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if (remainder >= 38400 * (3/4)) {
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divm = 4;
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divn = divn * divm + 3;
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} else
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if (remainder >= 38400 * (2/3)) {
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divm = 3;
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divn = divn * divm + 2;
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} else
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if (remainder >= 38400 * (1/2)) {
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divm = 2;
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divn = divn * divm + 1;
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} else
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if (remainder >= 38400 * (1/3)) {
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divm = 3;
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divn = divn * divm + 1;
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} else
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if (remainder >= 38400 * (1/4)) {
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divm = 4;
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divn = divn * divm + 1;
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}
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table->pllmb_divm = divm;
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table->pllmb_divn = divn;
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}
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#ifdef EXPERIMENTAL
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{
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#define ADJUST_PARAM_ROUND2_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM) \
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TARGET_TABLE->burst_regs.PARAM = \
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((ADJUST_PROP(TARGET_TABLE->burst_regs.PARAM, REF_TABLE->burst_regs.PARAM) + 1) >> 1) << 1; \
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TARGET_TABLE->shadow_regs_ca_train.PARAM = \
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((ADJUST_PROP(TARGET_TABLE->shadow_regs_ca_train.PARAM, REF_TABLE->shadow_regs_ca_train.PARAM) + 1) >> 1) << 1; \
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TARGET_TABLE->shadow_regs_rdwr_train.PARAM = \
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((ADJUST_PROP(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM) + 1) >> 1) << 1;
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#define ADJUST_PARAM(TARGET_PARAM, REF_PARAM) \
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TARGET_PARAM = ADJUST_PROP(TARGET_PARAM, REF_PARAM);
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#define ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, PARAM) \
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ADJUST_PARAM(TARGET_TABLE->PARAM, REF_TABLE->PARAM)
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#define ADJUST_PARAM_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM) \
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ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, burst_regs.PARAM) \
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ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, shadow_regs_ca_train.PARAM) \
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ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, shadow_regs_rdwr_train.PARAM)
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#define TRIM_BIT(IN_BITS, HIGH, LOW) \
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((IN_BITS >> LOW) & ( (1u << (HIGH - LOW + 1u)) - 1u ))
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#define ADJUST_BIT(TARGET_PARAM, REF_PARAM, HIGH, LOW) \
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ADJUST_PROP(TRIM_BIT(TARGET_PARAM, HIGH, LOW), TRIM_BIT(REF_PARAM, HIGH, LOW))
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#define CLEAR_BIT(BITS, HIGH, LOW) \
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BITS = BITS & ~( ((1u << HIGH) << 1u) - (1u << LOW) );
|
|
|
|
#define ADJUST_BIT_ALL_REG_SINGLE_OP(TARGET_TABLE, REF_TABLE, PARAM, HIGH, LOW, OPERATION) \
|
|
TARGET_TABLE->burst_regs.PARAM = \
|
|
(ADJUST_BIT(TARGET_TABLE->burst_regs.PARAM, REF_TABLE->burst_regs.PARAM, HIGH, LOW) << LOW) OPERATION; \
|
|
TARGET_TABLE->shadow_regs_ca_train.PARAM = \
|
|
(ADJUST_BIT(TARGET_TABLE->shadow_regs_ca_train.PARAM, REF_TABLE->shadow_regs_ca_train.PARAM, HIGH, LOW)) << LOW OPERATION; \
|
|
TARGET_TABLE->shadow_regs_rdwr_train.PARAM = \
|
|
(ADJUST_BIT(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM, HIGH, LOW)) << LOW OPERATION;
|
|
|
|
#define ADJUST_BIT_ALL_REG_PAIR(TARGET_TABLE, REF_TABLE, PARAM, HIGH1, LOW1, HIGH2, LOW2) \
|
|
TARGET_TABLE->burst_regs.PARAM = \
|
|
ADJUST_BIT(TARGET_TABLE->burst_regs.PARAM, REF_TABLE->burst_regs.PARAM, HIGH1, LOW1) << LOW1 \
|
|
| ADJUST_BIT(TARGET_TABLE->burst_regs.PARAM, REF_TABLE->burst_regs.PARAM, HIGH2, LOW2) << LOW2; \
|
|
TARGET_TABLE->shadow_regs_ca_train.PARAM = \
|
|
ADJUST_BIT(TARGET_TABLE->shadow_regs_ca_train.PARAM, REF_TABLE->shadow_regs_ca_train.PARAM, HIGH1, LOW1) << LOW1 \
|
|
| ADJUST_BIT(TARGET_TABLE->shadow_regs_ca_train.PARAM, REF_TABLE->shadow_regs_ca_train.PARAM, HIGH2, LOW2) << LOW2; \
|
|
TARGET_TABLE->shadow_regs_rdwr_train.PARAM = \
|
|
ADJUST_BIT(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM, HIGH1, LOW1) << LOW1 \
|
|
| ADJUST_BIT(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM, HIGH2, LOW2) << LOW2;
|
|
|
|
/* For latency allowance */
|
|
#define ADJUST_INVERSE(TARGET) ((TARGET*1000) / (EmcClock/1600))
|
|
|
|
/* emc_wdv, emc_wsv, emc_wev, emc_wdv_mask,
|
|
emc_quse, emc_quse_width, emc_ibdly, emc_obdly,
|
|
emc_einput, emc_einput_duration, emc_qrst, emc_qsafe,
|
|
emc_rdv, emc_rdv_mask, emc_rdv_early, emc_rdv_early_mask */
|
|
ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wdv);
|
|
ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wsv);
|
|
ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wev);
|
|
ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wdv_mask);
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_quse);
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_quse_width);
|
|
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_ibdly, 6,0, | (1 << 28));
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_obdly, 5,0, | (1 << 28));
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_einput);
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_einput_duration);
|
|
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_qrst, 6,0, | (6 << 16));
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_qsafe);
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rdv);
|
|
target_table->burst_regs.emc_rdv_mask = target_table->burst_regs.emc_rdv + 2;
|
|
target_table->shadow_regs_ca_train.emc_rdv_mask = target_table->shadow_regs_ca_train.emc_rdv + 2;
|
|
target_table->shadow_regs_rdwr_train.emc_rdv_mask = target_table->shadow_regs_rdwr_train.emc_rdv + 2;
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rdv_early);
|
|
target_table->burst_regs.emc_rdv_early_mask = target_table->burst_regs.emc_rdv_early + 2;
|
|
target_table->shadow_regs_ca_train.emc_rdv_early_mask = target_table->shadow_regs_ca_train.emc_rdv_early + 2;
|
|
target_table->shadow_regs_rdwr_train.emc_rdv_early_mask = target_table->shadow_regs_rdwr_train.emc_rdv_early + 2;
|
|
|
|
/* emc_pmacro_...,
|
|
emc_zcal_wait_cnt, emc_mrs_wait_cnt(2),
|
|
emc_pmacro_autocal_cfg_common, emc_dyn_self_ref_control, emc_qpop, emc_pmacro_cmd_pad_tx_ctrl,
|
|
emc_tr_timing_0, emc_tr_rdv, emc_tr_qpop, emc_tr_rdv_mask, emc_tr_qsafe, emc_tr_qrst,
|
|
emc_training_vref_settle */
|
|
/* DDLL values */
|
|
{
|
|
#define OFFSET_ALL_REG(PARAM) \
|
|
offsetof(MarikoMtcTable, burst_regs.PARAM), \
|
|
offsetof(MarikoMtcTable, shadow_regs_ca_train.PARAM), \
|
|
offsetof(MarikoMtcTable, shadow_regs_rdwr_train.PARAM) \
|
|
|
|
/* Section 1: adjust HI bits: BIT 26:16 */
|
|
const uint32_t ddll_high[] = {
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_5),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_5),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_5),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_0),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_1),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_2),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_3),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_4),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_0),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_1),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_2),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_3),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_4),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_5),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_0),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_1),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3),
|
|
};
|
|
for (uint32_t i = 0; i < sizeof(ddll_high)/sizeof(uint32_t); i++)
|
|
{
|
|
uint32_t *ddll = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(target_table) + ddll_high[i]);
|
|
uint32_t *ddll_ref = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(ref_table) + ddll_high[i]);
|
|
uint16_t adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 26,16) & ((1 << 10) - 1);
|
|
CLEAR_BIT(*ddll, 26,16)
|
|
*ddll |= adjusted_ddll << 16;
|
|
}
|
|
|
|
/* Section 2: adjust LOW bits: BIT 10:0 */
|
|
const uint32_t ddll_low[] = {
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_5),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_0),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_1),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_3),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_0),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_1),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_3),
|
|
OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank1_4),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_0),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_1),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_2),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_3),
|
|
OFFSET_ALL_REG(emc_pmacro_ddll_long_cmd_4),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_0),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_1),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_2),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_3),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_4),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_5),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_0),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_1),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2),
|
|
offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3),
|
|
};
|
|
for (uint32_t i = 0; i < sizeof(ddll_low)/sizeof(uint32_t); i++)
|
|
{
|
|
uint32_t *ddll = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(target_table) + ddll_low[i]);
|
|
uint32_t *ddll_ref = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(ref_table) + ddll_low[i]);
|
|
uint16_t adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 10,0) & ((1 << 10) - 1);
|
|
CLEAR_BIT(*ddll, 10,0)
|
|
*ddll |= adjusted_ddll;
|
|
}
|
|
}
|
|
|
|
ADJUST_BIT_ALL_REG_PAIR(target_table, ref_table, emc_zcal_wait_cnt, 21,16, 10,0)
|
|
ADJUST_BIT_ALL_REG_PAIR(target_table, ref_table, emc_mrs_wait_cnt, 21,16, 10,0)
|
|
ADJUST_BIT_ALL_REG_PAIR(target_table, ref_table, emc_mrs_wait_cnt2, 21,16, 10,0)
|
|
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_auto_cal_channel, 5,0, | 0xC1E00300)
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_pmacro_autocal_cfg_common, 5,0, | 8 << 8)
|
|
|
|
ADJUST_BIT_ALL_REG_PAIR(target_table, ref_table, emc_dyn_self_ref_control, 31,31, 15,0)
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_qpop);
|
|
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_tr_timing_0, 9,0, | 0x1186100)
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tr_rdv);
|
|
target_table->burst_regs.emc_tr_rdv_mask = target_table->burst_regs.emc_tr_rdv + 2;
|
|
target_table->shadow_regs_ca_train.emc_tr_rdv_mask = target_table->shadow_regs_ca_train.emc_tr_rdv + 2;
|
|
target_table->shadow_regs_rdwr_train.emc_tr_rdv_mask = target_table->shadow_regs_rdwr_train.emc_tr_rdv + 2;
|
|
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tr_qpop);
|
|
ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tr_qsafe);
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_tr_qrst, 6,0, | (6 << 16));
|
|
|
|
ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_training_vref_settle, 15,0, | (4 << 16));
|
|
|
|
/* External Memory Arbitration Configuration */
|
|
/* BIT 20:16 - EXTRA_TICKS_PER_UPDATE: 0 */
|
|
/* BIT 8:0 - CYCLES_PER_UPDATE: 12(1600MHz), 10(1331.2MHz) */
|
|
ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_cfg);
|
|
|
|
/* External Memory Arbitration Configuration: Direction Arbiter: Turns */
|
|
/* BIT 31:24 - W2R_TURN: approx. mc_emem_arb_timing_w2r */
|
|
/* BIT 23:16 - R2W_TURN: approx. mc_emem_arb_timing_r2w */
|
|
/* BIT 15:8 - W2W_TURN: 0 */
|
|
/* BIT 7:0 - R2R_TURN: 0 */
|
|
{
|
|
uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_da_turns;
|
|
uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_da_turns;
|
|
uint8_t w2r_turn = ADJUST_BIT(param_1600, param_1331, 31,24);
|
|
uint8_t r2w_turn = ADJUST_BIT(param_1600, param_1331, 23,16);
|
|
target_table->burst_mc_regs.mc_emem_arb_da_turns = w2r_turn << 24 | r2w_turn << 16;
|
|
}
|
|
|
|
/* External Memory Arbitration Configuration: Direction Arbiter: Covers */
|
|
/* BIT 23:16 - RCD_W_COVER: 13(1600MHz), 11(1331.2MHz) */
|
|
/* BIT 15:8 - RCD_R_COVER: 8(1600MHz), 7(1331.2MHz) */
|
|
/* BIT 7:0 - RC_COVER: approx. mc_emem_arb_timing_rc, 12(1600MHz), 9(1331.2MHz) */
|
|
{
|
|
uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_da_covers;
|
|
uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_da_covers;
|
|
uint8_t rcd_w_cover = ADJUST_BIT(param_1600, param_1331, 23,16);
|
|
uint8_t rcd_r_cover = ADJUST_BIT(param_1600, param_1331, 15,8);
|
|
uint8_t rc_cover = ADJUST_BIT(param_1600, param_1331, 7,0);
|
|
target_table->burst_mc_regs.mc_emem_arb_da_covers = rcd_w_cover << 16 | rcd_r_cover << 8 | rc_cover;
|
|
}
|
|
|
|
/* External Memory Arbitration Configuration: Miscellaneous Thresholds (0) */
|
|
/* BIT 20:16 - PRIORITY_INVERSION_ISO_THRESHOLD: 12(1600MHz), 10(1331.2MHz) */
|
|
/* BIT 14:8 - PRIORITY_INVERSION_THRESHOLD: 36(1600MHz), 30(1331.2MHz) */
|
|
/* BIT 7:0 - BC2AA_HOLDOFF_THRESHOLD: set to mc_emem_arb_timing_rc */
|
|
{
|
|
uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_misc0;
|
|
uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_misc0;
|
|
uint8_t priority_inversion_iso_threshold = ADJUST_BIT(param_1600, param_1331, 20,16);
|
|
uint8_t priority_inversion_threshold = ADJUST_BIT(param_1600, param_1331, 14,8);
|
|
uint8_t bc2aa_holdoff_threshold = target_table->burst_mc_regs.mc_emem_arb_timing_rc;
|
|
CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 20,16)
|
|
CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 14,8)
|
|
CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 7,0)
|
|
target_table->burst_mc_regs.mc_emem_arb_misc0 |=
|
|
(priority_inversion_iso_threshold << 16 | priority_inversion_threshold << 8 | bc2aa_holdoff_threshold);
|
|
}
|
|
|
|
/* Latency allowance settings */
|
|
{
|
|
/* Section 1: adjust write latency */
|
|
/* BIT 23:16 - ALLOWANCE_WRITE: 128(1600MHz), 153(1331.2MHz) */
|
|
const uint32_t latency_write_offset[] = {
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_xusb_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_xusb_1),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_tsec_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_sdmmca_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_sdmmcaa_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_sdmmc_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_sdmmcab_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_ppcs_1),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_mpcore_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_avpc_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_gpu_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_gpu2_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_nvenc_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_nvdec_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_vic_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_isp2_1),
|
|
};
|
|
for (uint32_t i = 0; i < sizeof(latency_write_offset)/sizeof(uint32_t); i++)
|
|
{
|
|
uint32_t *latency = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(target_table) + latency_write_offset[i]);
|
|
CLEAR_BIT(*latency, 23,16)
|
|
*latency |= ADJUST_INVERSE(128) << 16;
|
|
}
|
|
|
|
/* Section 2: adjust read latency */
|
|
/* BIT 7:0 - ALLOWANCE_READ */
|
|
const uint32_t latency_read_offset[] = {
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_hc_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_hc_1),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_gpu_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_gpu2_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_vic_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_vi2_0),
|
|
offsetof(MarikoMtcTable, la_scale_regs.mc_latency_allowance_isp2_1),
|
|
};
|
|
for (uint32_t i = 0; i < sizeof(latency_read_offset)/sizeof(uint32_t); i++)
|
|
{
|
|
uint32_t *latency = reinterpret_cast<uint32_t *>(reinterpret_cast<uint8_t *>(target_table) + latency_read_offset[i]);
|
|
uint8_t adjusted_latency = ADJUST_INVERSE(TRIM_BIT(*latency, 7,0));
|
|
CLEAR_BIT(*latency, 7,0)
|
|
*latency |= adjusted_latency;
|
|
}
|
|
}
|
|
|
|
/* PLLM and PLLMB control */
|
|
{
|
|
/*
|
|
* CLK_RST_CONTROLLER_PLLM_SS_CTRL1:
|
|
* BIT 31:16 : PLLM_SDM_SSC_MAX
|
|
* BIT 15:0 : PLLM_SDM_SSC_MIN
|
|
*
|
|
* CLK_RST_CONTROLLER_PLLM_SS_CTRL2:
|
|
* BIT 31:16 : PLLM_SDM_SSC_STEP
|
|
* BIT 15:0 : PLLM_SDM_DIN
|
|
*
|
|
* pllm(b)_ss_ctrl1:
|
|
* 1365, 342 (1600MHz)
|
|
* 0xFAAB, 0xF404 (1331MHz)
|
|
*
|
|
* pllm(b)_ss_ctrl2:
|
|
* 2, 1365 (1600MHz)
|
|
* 6, 0xFAAB (1331MHz)
|
|
*
|
|
* No need to care about this if Spread Spectrum (SS) is disabled
|
|
*/
|
|
// Disable PLL Spread Spectrum Control
|
|
table->pll_en_ssc = 0;
|
|
table->pllm_ss_cfg = 1 << 30;
|
|
}
|
|
|
|
/* EMC misc. configuration */
|
|
{
|
|
/* ? Command Trigger: MRW, MRW2: MRW_OP - [PMC] data to be written ?
|
|
*
|
|
* EMC_MRW: MRW_OP
|
|
* 1600 MHz: 0x54
|
|
* 1331 MHz: 0x44
|
|
* 1065 MHz: 0x34
|
|
* 800 MHz: 0x34
|
|
* 665 MHz: 0x14
|
|
* 408 MHz: 0x04
|
|
* 204 MHz: 0x04
|
|
*
|
|
* EMC_MRW2: MRW2_OP
|
|
* 1600 MHz: 0x2D 45 5*9
|
|
* 1331 MHz: 0x24 36 4*9
|
|
* 1065 MHz: 0x1B 27 3*9
|
|
* 800 MHz: 0x12 18 2*9
|
|
* 665 MHz: 0x09 9 1*9
|
|
* 408 MHz: 0x00
|
|
* 204 MHz: 0x00
|
|
*/
|
|
{
|
|
|
|
}
|
|
|
|
/* EMC_CFG_2 */
|
|
/* BIT 5:3 - ZQ_EXTRA_DELAY: 6(1600MHz), 5(1331.2MHz), max possible value: 7 */
|
|
{
|
|
CLEAR_BIT(target_table->emc_cfg_2, 5,3)
|
|
target_table->emc_cfg_2 |= 7 << 3;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#pragma GCC diagnostic ignored "-Wunused-variable"
|
|
void ApplyAutoPcvPatch(uintptr_t mapped_nso, size_t nso_size) {
|
|
/* Abort immediately once something goes wrong */
|
|
bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
|
|
|
|
constexpr u32 emcMaxClockMaxCnt = 30;
|
|
constexpr u32 cpuMaxVoltMarikoMaxCnt = 13;
|
|
constexpr u32 mtcTableMarikoMaxCnt = 13;
|
|
constexpr u32 gpuMaxClockMarikoReqCnt = 2;
|
|
|
|
constexpr u32 cpuClockVddCpuPatternNext = 0;
|
|
constexpr u32 cpuTableMarikoPatternNext = 1527196;
|
|
// constexpr u32 cpuTableEristaPatternNext = 1227500;
|
|
|
|
constexpr u32 cpuMinVolt[] = { 800, 637, 620, 610 };
|
|
|
|
u8 emcMaxClock {};
|
|
u8 cpuClockVddCpu {};
|
|
u8 cpuTableMariko {};
|
|
// u8 cpuTableErista {};
|
|
u8 gpuTableMariko {};
|
|
u8 cpuMaxVoltMariko {};
|
|
u8 mtcTableMariko {};
|
|
u8 dvbTableMariko {};
|
|
u8 gpuMaxClockMariko {};
|
|
u8 gpuMaxClockMarikoRd {};
|
|
u32 gpuMaxClockPattern[2] = { 0x528E0000, 0x72A002E0 }; // 1536 MHz
|
|
|
|
uintptr_t i = mapped_nso;
|
|
while (i <= mapped_nso + nso_size - sizeof(MarikoMtcTable))
|
|
{
|
|
u32 value = *(reinterpret_cast<u32 *>(i));
|
|
|
|
#ifdef EXPERIMENTAL
|
|
if (isMariko)
|
|
{
|
|
// CPU Table
|
|
if (value == 1785'000)
|
|
{
|
|
u32 value_next2 = *(reinterpret_cast<u32 *>(i + sizeof(u32) * 2));
|
|
if (value_next2 == cpuClockVddCpuPatternNext)
|
|
{
|
|
u32 value_next = *(reinterpret_cast<u32 *>(i + sizeof(u32)));
|
|
if (value_next == cpuClockVddCpuPatternNext)
|
|
{
|
|
std::memcpy(reinterpret_cast<void *>(i), &CpuMaxClock, sizeof(CpuMaxClock));
|
|
cpuClockVddCpu++;
|
|
}
|
|
}
|
|
|
|
if (value_next2 == cpuTableMarikoPatternNext)
|
|
{
|
|
uintptr_t entry_1963 = i + 2 * sizeof(cpu_freq_cvb_table_t);
|
|
uintptr_t free_space = entry_1963 + sizeof(cpu_freq_cvb_table_t);
|
|
uintptr_t entry_204 = free_space - 18 * sizeof(cpu_freq_cvb_table_t);
|
|
|
|
if ( *(reinterpret_cast<u32 *>(entry_1963)) == 1963'500
|
|
&& *(reinterpret_cast<u32 *>(free_space)) == 0
|
|
&& *(reinterpret_cast<u32 *>(entry_204)) == 204'000 )
|
|
{
|
|
std::memcpy(reinterpret_cast<void *>(free_space), NewCpuTables, sizeof(NewCpuTables));
|
|
cpuTableMariko++;
|
|
|
|
// Patch CPU max volt (1120'000) in CPU dvfs table
|
|
for (u32 i = 0; i < 18; i++)
|
|
{
|
|
void* max_volt_dvfs = reinterpret_cast<void *>(free_space - i * sizeof(cpu_freq_cvb_table_t) - sizeof(cvb_coefficients));
|
|
std::memcpy(max_volt_dvfs, &NewCpuVoltageScaled, sizeof(NewCpuVoltageScaled));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// GPU Table
|
|
if (value == 1267'200)
|
|
{
|
|
u32 free_space = i + sizeof(gpu_cvb_pll_table_t);
|
|
if (*(reinterpret_cast<u32 *>(free_space)) == 0)
|
|
{
|
|
std::memcpy(reinterpret_cast<void *>(free_space), NewGpuTables, sizeof(NewGpuTables));
|
|
gpuTableMariko++;
|
|
}
|
|
}
|
|
|
|
// CPU voltage range
|
|
if (value == 1120)
|
|
{
|
|
u32 value_cpu_min_volt = *(reinterpret_cast<u32 *>(i - sizeof(u32)));
|
|
|
|
for (u32 j = 0; j < sizeof(cpuMinVolt)/sizeof(u32); j++)
|
|
{
|
|
if (cpuMinVolt[j] == value_cpu_min_volt)
|
|
{
|
|
// acceptable cpu min volt, patch max volt
|
|
std::memcpy(reinterpret_cast<void *>(i), &CpuVoltageLimit, sizeof(CpuVoltageLimit));
|
|
cpuMaxVoltMariko++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// GPU Max Clock asm
|
|
{
|
|
// Pattern:
|
|
// *
|
|
// * MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
|
|
// * sf | opc | | hw | imm16 | Rd
|
|
// * #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
|
// * 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
|
|
// *
|
|
// * MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
|
|
// * sf | opc | | hw | imm16 | Rd
|
|
// * #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
|
// * 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
|
|
|
|
constexpr u32 mov_w_0x1000_hi = 0x52820000 >> 5;
|
|
constexpr u32 movk_w_0xE_shift16_hi = 0x72A001C0 >> 5;
|
|
|
|
u32 value_hi = value >> 5;
|
|
u32 value_lo = value & ((1 << 5) - 1);
|
|
if (value_hi == mov_w_0x1000_hi)
|
|
{
|
|
u32 value_next = *(reinterpret_cast<u32 *>(i + sizeof(u32)));
|
|
u32 value_next_hi = value_next >> 5;
|
|
u32 value_next_lo = value_next & ((1 << 5) - 1);
|
|
if (value_next_hi == movk_w_0xE_shift16_hi && value_next_lo == value_lo)
|
|
{
|
|
if (!gpuMaxClockMarikoRd)
|
|
gpuMaxClockMarikoRd = value_lo;
|
|
if (gpuMaxClockMarikoRd != value_lo)
|
|
AMS_ABORT("gpuMaxClockMarikoRd not consistent!");
|
|
|
|
gpuMaxClockPattern[0] |= gpuMaxClockMarikoRd;
|
|
gpuMaxClockPattern[1] |= gpuMaxClockMarikoRd;
|
|
|
|
std::memcpy(reinterpret_cast<void *>(i), gpuMaxClockPattern, sizeof(gpuMaxClockPattern));
|
|
gpuMaxClockMariko++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
{
|
|
// MEM
|
|
if (value == 1600'000)
|
|
{
|
|
if (isMariko)
|
|
{
|
|
u32 value_next = *(reinterpret_cast<u32 *>(i + sizeof(u32)));
|
|
u32 value_next2 = *(reinterpret_cast<u32 *>(i + sizeof(u32) * 2));
|
|
|
|
if (value_next == 1100) // min_volt in MtcTable
|
|
{
|
|
uintptr_t offset = i - offsetof(MarikoMtcTable, rate_khz);
|
|
uintptr_t offset_prev = offset - sizeof(MarikoMtcTable);
|
|
|
|
MarikoMtcTable* const mtc_table_new = reinterpret_cast<MarikoMtcTable *>(offset);
|
|
MarikoMtcTable* const mtc_table_old = reinterpret_cast<MarikoMtcTable *>(offset_prev);
|
|
if (mtc_table_new->rev != 3 || mtc_table_old->rev != 3 || mtc_table_old->rate_khz != 1331'200)
|
|
AMS_ABORT("mtc_table");
|
|
|
|
// Replace 1331 MHz with 1600 MHz
|
|
std::memcpy(reinterpret_cast<void *>(mtc_table_old), reinterpret_cast<void *>(mtc_table_new), sizeof(MarikoMtcTable));
|
|
mtcTableMariko++;
|
|
|
|
// Generate new table for Max MHz
|
|
// [!TODO] ref table is identical to new table, leaving some params unchanged
|
|
AdjustMtcTable(mtc_table_new, mtc_table_old);
|
|
}
|
|
else if (value_next2 == 675) // Mariko Dvb Table
|
|
{
|
|
u32 dvb_1331_offset = i - sizeof(emc_dvb_dvfs_table_t);
|
|
|
|
u32 value_1331_entry = *(reinterpret_cast<u32 *>(dvb_1331_offset));
|
|
if (value_1331_entry == 1331'200)
|
|
{
|
|
const u32 dvb_1600_clk = 1600'000;
|
|
std::memcpy(reinterpret_cast<void *>(dvb_1331_offset), &dvb_1600_clk, sizeof(dvb_1600_clk));
|
|
dvbTableMariko++;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Patch Max Emc Clock for both Erista and Mariko
|
|
std::memcpy(reinterpret_cast<void *>(i), &EmcClock, sizeof(EmcClock));
|
|
emcMaxClock++;
|
|
}
|
|
}
|
|
|
|
i += sizeof(u32);
|
|
}
|
|
|
|
if (isMariko)
|
|
{
|
|
// if (cpuClockVddCpu != 1)
|
|
// AMS_ABORT("cpuClockVddCpu");
|
|
// if (cpuTableMariko != 1)
|
|
// AMS_ABORT("cpuTableMariko");
|
|
// if (gpuTableMariko != 1)
|
|
// AMS_ABORT("gpuTableMariko");
|
|
if (dvbTableMariko != 1)
|
|
AMS_ABORT("dvbTableMariko");
|
|
// if (cpuMaxVoltMariko > cpuMaxVoltMarikoMaxCnt || !cpuMaxVoltMariko)
|
|
// AMS_ABORT("cpuMaxVoltMariko");
|
|
if (mtcTableMariko > mtcTableMarikoMaxCnt || !mtcTableMariko)
|
|
AMS_ABORT("mtcTableMariko");
|
|
// if (gpuMaxClockMariko != gpuMaxClockMarikoReqCnt)
|
|
// AMS_ABORT("gpuMaxClockMariko");
|
|
}
|
|
{
|
|
if (emcMaxClock > emcMaxClockMaxCnt || !emcMaxClock)
|
|
AMS_ABORT("emcMaxClock");
|
|
}
|
|
}
|
|
#pragma GCC diagnostic error "-Wunused-variable"
|
|
}
|
|
|
|
namespace ptm {
|
|
void ApplyAutoPtmPatch(uintptr_t mapped_nso, size_t nso_size) {
|
|
/* No abort here as ptm is not that critical */
|
|
if (spl::GetSocType() == spl::SocType_Erista)
|
|
return;
|
|
|
|
uintptr_t emcOffsetStart = 0;
|
|
constexpr u32 OffsetInterval = 0x20;
|
|
constexpr u32 emcOffsetCnt = 16;
|
|
constexpr u32 EmcMaxClk = EmcClock * 1000;
|
|
constexpr u32 Emc1600Clk = 1600'000'000;
|
|
|
|
uintptr_t i = mapped_nso;
|
|
|
|
while (i <= mapped_nso + nso_size)
|
|
{
|
|
u32 value = *(reinterpret_cast<u32 *>(i));
|
|
|
|
if (value == 1600'000'000)
|
|
{
|
|
emcOffsetStart = i;
|
|
break;
|
|
}
|
|
|
|
i += sizeof(u32);
|
|
}
|
|
|
|
if (!emcOffsetStart)
|
|
return;
|
|
|
|
for (u32 j = 0; j < emcOffsetCnt; j++)
|
|
{
|
|
uintptr_t offset = emcOffsetStart + OffsetInterval * j;
|
|
uintptr_t offset_next = offset + sizeof(u32);
|
|
|
|
if (offset_next > mapped_nso + nso_size)
|
|
return;
|
|
|
|
u32 value = *(reinterpret_cast<u32 *>(offset));
|
|
u32 value_next = *(reinterpret_cast<u32 *>(offset_next));
|
|
|
|
if (value != value_next)
|
|
return;
|
|
|
|
u32 value_patched = value;
|
|
|
|
switch (value)
|
|
{
|
|
case 1600'000'000:
|
|
value_patched = EmcMaxClk;
|
|
break;
|
|
case 1331'200'000:
|
|
case 1065'600'000:
|
|
value_patched = Emc1600Clk;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
std::memcpy(reinterpret_cast<void *>(offset), &value_patched, sizeof(value_patched));
|
|
std::memcpy(reinterpret_cast<void *>(offset_next), &value_patched, sizeof(value_patched));
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|