51 lines
1.5 KiB
Makefile
51 lines
1.5 KiB
Makefile
TARGET_EXEC := test
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BUILD_DIR := ./build
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SRC_DIRS := ./
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# CXX := clang++ g++-12
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# Find all the C and C++ files we want to compile
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# Note the single quotes around the * expressions. Make will incorrectly expand these otherwise.
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SRCS := $(shell find $(SRC_DIRS) -name '*.cpp' -or -name '*.c' -or -name '*.s')
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# String substitution for every C/C++ file.
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# As an example, hello.cpp turns into ./build/hello.cpp.o
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OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
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# String substitution (suffix version without %).
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# As an example, ./build/hello.cpp.o turns into ./build/hello.cpp.d
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DEPS := $(OBJS:.o=.d)
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# Every folder in ./src will need to be passed to GCC so that it can find header files
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INC_DIRS := $(shell find $(SRC_DIRS) -type d)
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# Add a prefix to INC_DIRS. So moduleA would become -ImoduleA. GCC understands this -I flag
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INC_FLAGS := $(addprefix -I,$(INC_DIRS))
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CPPFLAGS := $(INC_FLAGS) -Wall -Werror -Wno-unused-result -std=c++20 -Og -g
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# The final build step.
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$(TARGET_EXEC): $(OBJS)
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@echo "Linking $@"
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@$(CXX) $(OBJS) -o $@ $(LDFLAGS)
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# Build step for C source
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$(BUILD_DIR)/%.c.o: %.c
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@mkdir -p $(dir $@)
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@echo "$<"
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@$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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# Build step for C++ source
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$(BUILD_DIR)/%.cpp.o: %.cpp
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@mkdir -p $(dir $@)
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@echo "$<"
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@$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c $< -o $@
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.PHONY: clean
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clean:
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@rm -r $(BUILD_DIR) $(TARGET_EXEC)
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# Include the .d makefiles. The - at the front suppresses the errors of missing
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# Makefiles. Initially, all the .d files will be missing, and we don't want those
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# errors to show up.
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-include $(DEPS) |